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mc68lc302 low power integrated multiprotocol processor reference manual microprocessors and memory technologies group literature distribution centers: usa/europe: motorola literature distribution; p.o. box 20912, arizona 85036. japan: nippon motorola ltd.; 4-32-1, nishi-gotanda, shinagawa-ku, tokyo 141 japan. asia-pacific: motorola semiconductors h.k. ltd.; silicon harbour center, no. 2 dai king street, tai po industrial estate, motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "typical" parameters can and do vary in different applications. all operating parameters, including "typicals" must be validated for each customer application by customer's technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer.
iii mc68lc302 reference manual motorola preface the complete documentation package for the mc68lc302 consists of the mc68lc302rm/ ad, mc68lc302 low power integrated multiprotocol processor reference manual , m68000pm/ad, mc68000 family programmer? reference manual, mc68302um/ad, mc68302 integrated multiprotocol processor user? manual, and the mc68lc302/d, mc68lc302 low power integrated multiprotocol processor product brief . the mc68lc302 low power integrated multiprotocol processor reference manual de- scribes the programming, capabilities, registers, and operation of the mc68lc302 that differ from the original mc68302; the mc68000 family programmer? reference manual provides instruction details for the mc68lc302; and the mc68lc302 low power integrated multipro- tocol processor product brief provides a brief description of the mc68lc302 capabilities. the mc68302 integrated multiprotocol processor user? manual is required, since the mc68lc302 low power integrated multiprotocol processor reference manual only de- scribes the new features of the mc68lc302. this user? manual is organized as follows: section 1 introduction section 2 configuration, clocking, low power modes, and internal memory map section 3 system integration block (sib) section 4 communications processor (cp) section 5 signal description section 6 electrical characteristics section 7 mechanical data and ordering information electronic support: the technical support bbs, known as aesop (application engineering support through on-line productivity), can be reach by modem or the internet. aesop provides commonly asked application questons, latest device errata, device specs, software code, and many other useful support functions. modem: call 1-800-843-3451 (outside us or canada 512-891-3650) on a modem that runs at 14,400 bps or slower. set your software to n/8/1/f emulating a vt100. internet: this access is provided by telneting to pirs.aus.sps.mot.com [129.38.233.1] or through the world wide web at http://pirs.aus.sps.mot.com. sales offices for questions or comments pertaining to technical information, questions, and applications, please contact one of the following sales offices nearest you.
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motorola mc68lc302 reference manual v table of contents paragraph title page number number section 1 introduction 1.1 block diagram......................................................................................... 1-1 1.2 features .................................................................................................. 1-2 1.3 lc302 applications ................................................................................. 1-3 1.4 lc302 differences .................................................................................. 1-3 section 2 configuration, clocking, low power modes, and internal memory map 2.1 mc68lc302 and mc68302 signal differences ...................................... 2-1 2.2 imp configuration control....................................................................... 2-2 2.2.1 base address register ........................................................................... 2-4 2.3 system configuration registers.............................................................. 2-5 2.4 clock generation and low power control .............................................. 2-5 2.4.1 pll and oscillator changes to imp ........................................................ 2-5 2.4.1.1 clock control register ............................................................................ 2-6 2.4.2 mc68lc302 system clock generation .................................................. 2-6 2.4.2.1 default system clock generation ........................................................... 2-7 2.4.3 imp system clock generation ................................................................ 2-8 2.4.3.1 system clock configuration.................................................................... 2-8 2.4.3.2 on-chip oscillator................................................................................... 2-8 2.4.3.3 phase-locked loop (pll) ...................................................................... 2-9 2.4.3.4 frequency multiplication ......................................................................... 2-9 2.4.3.4.1 low power pll clock divider............................................................... 2-10 2.4.3.4.2 imp pll and clock control register (iplcr) ...................................... 2-10 2.4.3.5 imp internal clock signals .................................................................... 2-12 2.4.3.5.1 imp system clock................................................................................. 2-12 2.4.3.5.2 brg clock ............................................................................................ 2-12 2.4.3.5.3 pit clock............................................................................................... 2-12 2.4.3.6 imp pll pins ........................................................................................ 2-12 2.4.3.6.1 vccsyn ............................................................................................... 2-12 2.4.3.6.2 gndsyn............................................................................................... 2-12 2.4.3.6.3 xfc ....................................................................................................... 2-12 2.4.3.6.4 modclk............................................................................................... 2-12 2.4.4 imp power management....................................................................... 2-13 2.4.4.1 imp low power modes ......................................................................... 2-13 2.4.4.1.1 stop mode .......................................................................................... 2-13 2.4.4.1.2 doze mode .......................................................................................... 2-13 2.4.4.1.3 stand_by mode ................................................................................. 2-13
table of contents paragraph title page number number vi mc68lc302 reference manual motorola 2.4.4.1.4 slow_go mode...................................................................................2-14 2.4.4.1.5 normal mode......................................................................................2-14 2.4.4.1.6 imp operation mode control register (iomcr) ...................................2-14 2.4.4.1.7 low power drive control register (lpdcr) .........................................2-15 2.4.4.1.8 imp power down register (ipwrd) .....................................................2-15 2.4.4.1.9 default operation modes. ......................................................................2-15 2.4.4.2 low power support................................................................................2-15 2.4.4.2.1 enter the slow_go mode ...................................................................2-15 2.4.4.2.2 entering the stop/ doze/ stand_by mode......................................2-16 2.4.4.2.3 imp wake-up from low power stop modes .......................................2-17 2.4.4.2.4 imp wake-up control register (iwucr) ..............................................2-17 2.4.4.3 fast wake-up ........................................................................................2-18 2.4.4.3.5 ring oscillator control register (ringocr) ........................................2-19 2.4.4.3.6 ring oscillator event register (ringoevr). .......................................2-20 2.5 mc68lc302 dual port ram..................................................................2-20 2.6 internal registers map...........................................................................2-23 section 3 system integration block (sib) 3.1 system control ........................................................................................3-1 3.1.1 system control register (scr) ...............................................................3-2 3.1.2 system status bits...................................................................................3-3 3.1.3 system control bits .................................................................................3-3 3.1.4 freeze control .........................................................................................3-5 3.1.5 hardware watchdog ................................................................................3-5 3.2 programmable data bus size switch ......................................................3-6 3.2.1 bus switch register (bsr) ......................................................................3-6 3.2.2 basic procedure:......................................................................................3-6 3.3 load boot code from an scc.................................................................3-7 3.4 dma control ..........................................................................................3-10 3.4.1 mc68lc302 differences........................................................................3-10 3.4.2 idma registers (independent dma controller).....................................3-11 3.4.2.1 channel mode register (cmr)..............................................................3-11 3.4.2.2 source address pointer register (sapr) .............................................3-13 3.4.2.3 destination address pointer register (dapr).......................................3-13 3.4.2.4 function code register (fcr) ..............................................................3-13 3.4.2.5 byte count register (bcr)....................................................................3-13 3.4.2.6 channel status register (csr) .............................................................3-13 3.5 interrupt controller .................................................................................3-14 3.5.1 interrupt controller key differences.......................................................3-14 3.5.2 interrupt controller programming model................................................3-14 3.5.2.1 global interrupt mode register (gimr) .................................................3-14 3.5.2.2 interrupt pending register (ipr)............................................................3-15 3.5.2.3 interrupt mask register (imr)................................................................3-16 3.5.2.4 interrupt in-service register (isr).........................................................3-16
table of contents paragraph title page number number motorola mc68lc302 reference manual vii 3.6 parallel i/o ports ................................................................................... 3-17 3.6.1 parallel i/o port differences.................................................................. 3-17 3.6.2 port a .................................................................................................... 3-17 3.6.3 port b .................................................................................................... 3-18 3.6.3.1 pb7?b3............................................................................................... 3-18 3.6.3.2 pb11?b8............................................................................................. 3-18 3.6.4 port n .................................................................................................... 3-19 3.6.5 port registers........................................................................................ 3-19 3.7 timers ................................................................................................... 3-20 3.7.1 mc68lc302 general purpose timer difference .................................. 3-20 3.7.2 general purpose timers programming mode....................................... 3-20 3.7.2.1 timer mode register (tmr1, tmr2).................................................... 3-20 3.7.2.2 timer reference registers (trr1, trr2) ........................................... 3-21 3.7.2.3 timer capture registers (tcr1, tcr2) ............................................... 3-21 3.7.2.4 timer counter (tcn1, tcn2) ............................................................... 3-21 3.7.2.5 timer event registers (ter1, ter2) ................................................... 3-21 3.7.3 timer 3 - software watchdog timer ..................................................... 3-22 3.7.3.1 software watchdog reference register (wrr) ................................... 3-22 3.7.3.2 software watchdog counter (wcn) ..................................................... 3-22 3.7.4 periodic interrupt timer (pit)................................................................ 3-22 3.7.4.1 overview ............................................................................................... 3-23 3.7.4.2 periodic timer period calculation ......................................................... 3-23 3.7.4.3 using the periodic timer as a real-time clock ................................... 3-24 3.7.4.4 periodic interrupt timer register (pitr)............................................... 3-24 3.8 external chip-select signals and wait-state logic .............................. 3-25 3.8.1 chip-select registers............................................................................ 3-26 3.8.1.1 base register (br3?r0) .................................................................... 3-26 3.8.1.2 option registers (or3?r0) ............................................................... 3-26 3.8.2 disable cpu logic (m68000)................................................................ 3-28 3.8.3 bus arbitration logic ............................................................................. 3-28 3.8.3.1 internal bus arbitration.......................................................................... 3-28 3.8.3.2 external bus arbitration......................................................................... 3-28 3.9 dynamic ram refresh controller ......................................................... 3-29 section 4 communications processor (cp) 4.1 mc68lc302 key differences from the mc68302 ................................... 4-1 4.2 serial channels physical interface.......................................................... 4-2 4.2.1 serial interface registers ........................................................................ 4-2 4.2.1.1 serial interface mode register (simode) .............................................. 4-2 4.2.1.2 serial interface mask register (simask) ............................................... 4-4 4.3 serial communication controllers (sccs) .............................................. 4-4 4.3.1 scc configuration register (scon) ...................................................... 4-4 4.3.1.1 divide by 2 input blocks (new feature) .................................................. 4-4 4.3.2 disable scc1 serial clocks out (disc) ................................................. 4-4 4.3.2.1 rclk1 and tclk1 pin options .............................................................. 4-5
table of contents paragraph title page number number viii mc68lc302 reference manual motorola 4.3.3 scc mode register (scm)......................................................................4-5 4.3.4 scc data synchronization register (dsr).............................................4-6 4.3.5 buffer descriptors table ..........................................................................4-6 4.3.6 scc parameter ram memory map.........................................................4-7 4.3.7 interrupt mechanism ................................................................................4-7 4.3.8 uart controller.......................................................................................4-7 4.3.8.1 uart memory map .................................................................................4-7 4.3.8.2 uart mode register...............................................................................4-8 4.3.8.3 uart receive buffer descriptor (rx bd) ...............................................4-8 4.3.8.4 uart transmit buffer descriptor (tx bd)...............................................4-8 4.3.8.5 uart event register...............................................................................4-9 4.3.8.6 uart mask register..............................................................................4-9 4.3.9 autobaud controller (new) ......................................................................4-9 4.3.9.1 autobaud channel reception process ....................................................4-9 4.3.9.2 autobaud channel transmit process ....................................................4-11 4.3.9.3 autobaud parameter ram.....................................................................4-11 4.3.9.4 autobaud programming model ..............................................................4-13 4.3.9.4.1 preparing for the autobaud process......................................................4-13 4.3.9.4.2 enter_baud_hunt command.................................................................4-14 4.3.9.4.3 autobaud command descriptor.............................................................4-14 4.3.9.4.4 autobaud lookup table.........................................................................4-15 4.3.9.5 lookup table example ..........................................................................4-17 4.3.9.6 determining character length and parity..............................................4-17 4.3.9.7 autobaud reception error handling procedure.....................................4-18 4.3.9.8 autobaud transmission .........................................................................4-18 4.3.9.8.1 automatic echo......................................................................................4-19 4.3.9.8.2 smart echo ............................................................................................4-19 4.3.9.9 reprogramming to uart mode or another protocol ............................4-20 4.3.10 hdlc controller.....................................................................................4-20 4.3.10.1 hdlc memory map ...............................................................................4-20 4.3.10.2 hdlc mode register.............................................................................4-20 4.3.10.3 hdlc receive buffer descriptor (rx bd) .............................................4-21 4.3.10.4 hdlc transmit buffer descriptor (tx bd).............................................4-21 4.3.10.5 hdlc event register.............................................................................4-21 4.3.10.6 hdlc mask register .............................................................................4-21 4.3.11 bisync controller .................................................................................4-22 4.3.11.1 bisync memory map............................................................................4-22 4.3.11.2 bisync mode register .........................................................................4-22 4.3.11.3 bisync receive buffer descriptor (rx bd)..........................................4-22 4.3.11.4 bisync transmit buffer descriptor (tx bd). ........................................4-22 4.3.11.5 bisync event register .........................................................................4-23 4.3.11.6 bisync mask register..........................................................................4-23 4.3.12 transparent controller ...........................................................................4-23 4.3.12.1 transparent memory map......................................................................4-23 4.3.12.2 transparent mode register ...................................................................4-24
table of contents paragraph title page number number motorola mc68lc302 reference manual ix 4.3.12.3 transparent receive buffer descriptor (rxbd) .................................... 4-24 4.3.12.4 transparent transmit buffer descriptor (tx bd)................................... 4-25 4.3.12.5 transparent event register .................................................................. 4-25 4.3.12.6 transparent mask register ................................................................... 4-25 4.4 serial communication port (scp)......................................................... 4-25 4.4.1 scp programming model...................................................................... 4-25 4.4.2 scp transmit/receive buffer descriptor .............................................. 4-26 4.5 serial management controllers (smcs)................................................ 4-26 4.5.1 smc programming model ..................................................................... 4-26 4.5.2 smc memory structure and buffers descriptors .................................. 4-26 4.5.2.1 smc1 receive buffer descriptor .......................................................... 4-26 4.5.2.2 smc1 transmit buffer descriptor ......................................................... 4-26 4.5.2.3 smc2 receive buffer descriptor .......................................................... 4-27 4.5.2.4 smc2 transmit buffer descriptor ......................................................... 4-27 section 5 signal description 5.1 functional groups ................................................................................... 5-1 5.2 power pins .............................................................................................. 5-2 5.3 clock pins ............................................................................................... 5-4 5.4 system control pins................................................................................ 5-5 5.5 address bus pins (a19?1).................................................................... 5-7 5.6 data bus pins (d15?0) ....................................................................... 5-8 5.7 bus control pins...................................................................................... 5-9 5.8 bus arbitration pins............................................................................... 5-10 5.9 interrupt control pins ............................................................................ 5-11 5.10 mc68lc302 bus interface signal summary......................................... 5-12 5.11 physical layer serial interface pins...................................................... 5-14 5.12 typical serial interface pin configurations ........................................... 5-14 5.13 nmsi1 or isdn interface pins............................................................... 5-14 5.14 nmsi2 port or port a pins ..................................................................... 5-17 5.15 paio / scp pins ................................................................................... 5-18 5.16 timer pins ............................................................................................. 5-19 5.17 parallel i/o pins with interrupt capability .............................................. 5-20 5.18 chip-select pins.................................................................................... 5-21 5.19 when to use pullup resistors............................................................... 5-21 section 6 electrical characteristics 6.1 maximum ratings.................................................................................... 6-2 6.2 thermal characteristics .......................................................................... 6-2 6.3 power considerations ............................................................................. 6-3 6.4 power dissipation.................................................................................... 6-4 6.5 dc electrical characteristics................................................................... 6-5 6.6 dc electrical characteristics?msi1 in idl mode................................ 6-6 6.7 ac electrical specifications?lock timing ............................................ 6-6
table of contents paragraph title page number number x mc68lc302 reference manual motorola 6.7.1 ac electrical characteristics - imp phased lock loop (pll) characteristics .........................................................................................6-7 6.8 ac electrical specifications?mp bus master cycles ............................6-8 6.9 ac electrical specifications?ma .......................................................6-13 6.10 ac electrical specifications?xternal master internal asynchronous read/write cycles ............................................6-16 6.11 ac electrical specifications?xternal master internal synchronous read/write cycles .................................................................................6-19 6.12 ac electrical specifications?nternal master internal read/write cycles ....................................................................................................6-23 6.13 ac electrical specifications?hip-select timing internal master .......6-24 6.14 ac electrical specifications?hip-select timing external master .......6-25 6.15 ac electrical specifications?arallel i/o .............................................6-26 6.16 ac electrical specifications?nterrupts ...............................................6-26 6.17 ac electrical specifications?imers.....................................................6-28 6.18 ac electrical specifications?erial communications port ...................6-29 6.19 ac electrical specifications?dl timing) .............................................6-30 6.20 ac electrical specifications?ci timing .............................................6-32 6.21 ac electrical specifications?cm timing............................................6-34 6.22 ac electrical specifications?msi timing...........................................6-36 section 7 mechanical data and ordering information 7.1 pin assignments ......................................................................................7-1 7.1.1 pin grid array (pga) ...............................................................................7-1 7.1.2 surface mount (tqfp )............................................................................7-2 7.2 package dimensions ...............................................................................7-3 7.2.1 pin grid array (pga) ...............................................................................7-3 7.2.2 surface mount (tqfp).............................................................................7-4 7.3 ordering information ................................................................................7-5
motorola mc68lc302 reference manual 1-1 section 1 introduction motorola has developed a low-cost version of the well-known mc68302 integrated multipro- tocol processor (imp) called the mc68lc302. simply put, the lc302 is a traditional 68302 minus the third serial communication controller (scc3) and has a new static 68000 core, a new timer and low power modes. it is packaged in a low profile 100 tqfp that reduces board space from the regular 68302, as well as making it suitable for use in height restricted applications such as pcmcia. the document fully describes all the differences between the lc302 and the regular 68302. any feature not described in this document will operate as described in the mc68302 user? manual . in addition this document contains the full set of electrical descriptions for the lc302, even though most of them are exactly the same as the 68302. 1.1 block diagram the block diagram is shown in figure 1-1. figure 1-1. mc68lc302 block diagram peripheral bus 68000 system bus 4 sdma channels interrupt controller risc controller static m68000 core 1 general- purpose dma channel 3 timers 4 chip selects pio system control ram / rom scp + 2 smcs 1152 bytes dual-port ram 2 serial channels (sccs) pit low power control 20 address 8/16 data 68lc302
introduction 1-2 mc68lc302 reference manual motorola 1.2 features the features of the lc302 are as follows. the items in bold face type show major differenc- es from the mc68302, although a complete list of differences is given in 1.4 lc302 differ- ences. on-chip static 68000 core supporting a 16- or 8-bit m68000 family-system sib including: independent direct memory access (idma) controller. interrupt controller with two modes of operation parallel input/output (i/o) ports, some with interrupt capability parallel input/output (i/o) ports on d15-d8 in 8 bit mode on-chip 1152-byte dual-port ram three timers including a watchdog timer new periodic interrupt timer (pit) four programmable chip-select lines with wait-state generator logic programmable address mapping of the dual-port ram and imp registers on-chip clock generator with output signal on-chip pll allows operation with 32khz or 4mhz crystals glueless interface to eprom, sram, flash eprom, and eeprom allows boot in 8-bit mode, and running switch to 16-bit mode system control: system status and control logic disable cpu logic (slave mode operation) hardware watchdog new low-power (standby) modes with wake-up from 2 pins or pit freeze control for debugging (available only in the pga package) dram refresh controller cp including: main controller (risc processor) two independent full-duplex serial communications controllers (sccs) supporting various protocols: high-level/synchronous data link control (hdlc/sdlc) universal asynchronous receiver transmitter (uart) binary synchronous communication (bisync) transparent modes autobaud support instead of ddcmp and v.110 boot from scc capability
introduction motorola mc68lc302 reference manual 1-3 four serial dma channels for the two sccs flexible physical interface accessible by sccs including: motorola interchip digital link (idl) general circuit interface (gci, also known as iom 1 -2) pulse code modulation (pcm) highway interface nonmultiplexed serial interface (nmsi) implementing standard modem signals scp for synchronous communication two serial management controllers (smcs) to support idl and gci auxiliary channels 100 pin thin quad flat pack (tqfp) packaging 1.3 lc302 applications the lc302 excels in several applications areas. first, any application using the 68302, but not needing all three serial channels is a potential candidate for the lc302. note however, that the lc302 sacrifices most of the provision for external bus mastership, thus the lc302 may not be appropriate where the 68302 is used as part of larger systems. second, the lc302 excels in low power and portable applications. the inclusion of a static 68000 core coupled with the low power modes built into the device make it ideal for hand- held, or other low power applications. the new 32 khz or 4 mhz pll option greatly reduces the total power budget of the designer? board, and allows the lc302 to be an effective device in low power systems. the lc302 can then optionally generate a full frequency clock for use by the rest of the board. during low power modes, the new periodic interrupt timer (pit) allows the device to be woken up at regular intervals. in addition, two pins allow the device to be woken up from low power modes. third, given that the lc302 is packaged in a 100tqfp package, it allows the 68302 to be used in space critical applications, as well as height critical applications such as pcmcia cards. fourth, since the disable cpu mode (also known as slave mode) is still retained, the lc302 can function as a fully intelligent dma-driven peripheral chip containing serial channels, tim- ers, and chip selects, etc. 1.4 lc302 differences the lc302 has some specific differences from the 68302. most of these differences simply result from the reduction in pins from 132 on the original 68302, to 100 pins on the lc302. 1. iom is a trademark of siemens ag
introduction 1-4 mc68lc302 reference manual motorola the following features have been removed or modified from the 68302 in order to make the lc302 possible. scc3 and its baud rate generator (brg3) are removed. external masters are not able to take the bus away from the lc302 except through a simple scheme using the halt pin. this restriction does not apply to using the lc302 in cpu disabled mode (slave mode), in which case br, bg, and bgack are all avail- able (they replace the ipl2-0 pins). although the independent dma (idma) is still available, the external idma request pins (dreq, dack, and done) have been eliminated. four address lines have been eliminated, giving a total of 20 address lines. however, the lc302 supports more than a 1 mb addressing range, since each of the four chip selects still decodes a 24-bit address. this allows a total of 4 mb to be addressed. since the function code pins and avec have been removed, interrupt acknowledgment to external devices is only provided on levels one, six, and seven. the ddcmp and v.110 protocols have been removed. the total list of pins removed is: a23-a20, fc2-fc0 ? , avec ? , rmc, iac ? , berr, br, bg, bgack, bclr, iack1, iack6, iack7, dreq, dack, done, brg1, frz ? , tout1, nc1, nc3, tclk3, rts3, cts3, cd3, plus 5 power and ground pins. note signals marked with ? are available in the pga package. the scp pins are now muxed with pa8, pa9, and pa10. the txd3, rxd3, and rclk3 functions associated with scc3 are eliminated. the uds, lds, and r/w pins are not available except in slave mode, where they re- place the weh, wel, and oe pins. instead, the new pins weh, wel, and oe have been defined for glueless interfacing to memory. pa12 is now muxed with the modclk pin, which is associated with the 32 khz or 4 mhz pll. the modclk pin is sampled after reset, and then becomes pa12. new vccsyn, gndsyn, and xfc pins have been added in support of the on-chip pll. for purposes of emulation support only, a special 132 pga version is supported. this version adds back the fc2-0, iac, frz, and avec pins. the fc2-0 pins allow bus cy- cles to be distinguished between program and data accesses, interrupt cycles, etc. the iac, frz, and avec pins are provided so that emulation vendors can quickly retrofit their existing 68302 emulator designs to support the lc302.
motorola mc68lc302 reference manual 2-1 section 2 configuration, clocking, low power modes, and internal memory map the mc68lc302 integrates a high-s/peed m68000 processor with multiple communications peripherals. the provision of direct memory access (dma) control and link layer manage- ment with the serial ports allows high throughput of data for communications-intensive appli- cations, such as basic rate integrated services digital network (isdn). the mc68lc302 can operate either in the full mc68000 mode with a 16-bit data bus or in the mc68008 mode with an 8-bit data bus by connecting the bus width (busw) pin low. note the busw pin is static and is not intended to be used for dy- namic bus sizing. instead the bsw and bswen bits in the bsr register should be used to switch the bus width after reset (3.2 programmable data bus size switch). if the state of the busw pin is changed during operation of the mc68lc302, erratic op- eration may occur. refer to the mc68000um/ad, m68000 8-/16-/32-bit microprocessors user's manual , and the mc68302um/ad, mc68302 integrated multiprotocol processor user? manual , for com- plete details of the on-chip microprocessor including the programming model and instruction set summary. throughout this manual, references may use the notation m68000, meaning all devices belonging to this family of microprocessors, or the notation mc68000, mc68008, meaning the specific microprocessor products. this section is intended to describe configuration of the mc68lc302 and the differences between thelc302 and the mc68000 and the mc68302.this section also includes tables that show the registers of the imp portion of the mc68lc302. all of the registers are memory mapped into the 68000 space 2.1 mc68lc302 and mc68302 signal differences the mc68lc302 in cpu enable mode has write enable (we ) signals instead of uds and lds signal. the write enable high (weh /a0) signal indicates that most significant data byte will be accessed, and the write enable low (wel /ds) indicates that the least significant data byte will be accessed. when the core is disabled, weh /a0 and wel /ds become uds/ a0 and lds/ds respectively.
configuration, clocking, low power modes, and internal memory map 2-2 mc68lc302 reference manual motorola the mc68lc302 in cpu enable mode has an output enable (oe ) signal instead of r/w . the oe signal indicates that the mc68lc302 expects an external device to drive data onto the data bus. when the core is disabled, oe becomes the r/w signal. the mc68lc302 in cpu enable mode does not have br , bg , and bgack pins. instead the halt pin is used to force the mc68lc302 off of the bus (see the halt signal descrip- tion in 5.4 system control pins). while the mc68lc302 is halted, the chip selects are still functional. the external master will not be able to access the internal registers and dual-port ram. when the core is disabled, the ipl0 , ipl1 , and ipl2 lines become the br , bg , and bgack signals. the only external interrupts handled are pb8, pb9, pb10, and pb11. two m6800 signals are omitted from the 68lc302: valid memory address (vma ) and enable (e). the valid peripheral address (vpa ) signal which was used on the mc68302 as avec has been removed from the mc68lc302. the signals for the serial communications port (scp) have been multiplexed with the pa8, pa9, and pa10 pins and the signals for scc3 have been removed. the fc2-0 pins have been removed from the mc68lc302. these signals are still driven internally by the core depending on the type of bus cycle (i.e. supervisor program space, supervisor data space, etc.) and the internal peripherals. they can still be used for address comparison in the chip select registers. in disable cpu mode and when halt is asserted for external masters, the fc signals are internally driven to 5 for external master accesses to internal peripherals. the a23-a20 pins have been removed from the mc68lc302. these signals are still driven internally by the core and the internal peripherals. the user must program the full 24-bit address in the chip select base registers, option registers, and in the pointers used by the internal dma and sccs. in disable cpu mode and when halt is asserted for external mas- ters, the a23-20 signals are driven to zero for all external master accesses. the other signals removed from the mc68lc302 are iac, rmc , blcr , berr , frz , brg1, dreq /pa13, dack /pa14, done /pa15, iack7 /pb0, iack6 /pb1, iack7 /pb2, and tout1 /pb4. the signals xfc and modclk (multiplexed with pa12) have been added for use with the on-chip phase lock loop. for purposes of emulation support only, a special 132 pga version is supported. this ver- sion adds back the fc2-0, iac, f rz , and avec pins. 2.2 imp configuration control a number of reserved entries in the external m68000 exception vector table are used as addresses for the internal system configuration registers. see table 2-1.
configuration, clocking, low power modes, and internal memory map motorola mc68lc302 reference manual 2-3 the bar entry contains the bar described in this section. the scr entry contains the scr described in section 3 system integration block (sib). figure 2-1 shows all the imp on-chip addressable locations and how they are mapped into system memory. the on-chip peripherals, including those peripherals in both the communications processor (cp) and system integration block (sib), require a 4k-byte block of address space. this 4k- byte block location is determined by writing the intended base address to the bar in super- visor data space (fc = 5). the fc2-0 pins are internally driven by the mc68lc302 to super- visor data space. after a total system reset, the on-chip peripheral base address is undefined, and it is not possible to access the on-chip peripherals at any address until bar is written. the bar and the scr can always be accessed at their fixed addresses. note the bar and scr registers are internally reset only when a to- tal system reset occurs by the simultaneous assertion of reset figure 2-1. imp configuration control $0f0 $0f4 $0f8 $0fb bar entry scr entry imp mode control imp power down imp system ram (dual-port) parameter ram (dual-port) internal registers base + $0 base + $400 base + $800 system memory map $0 base + $fff $3ff $xxx000 = base $ffffff 4k block bar points to the base 4k block 256 vector entries exception vector table pitr $0f2 $0f7 $0fa wake-up imp pll
configuration, clocking, low power modes, and internal memory map 2-4 mc68lc302 reference manual motorola and halt . the chip-select (cs ) lines are not asserted on ac- cesses to these locations. thus, it is very helpful to use cs lines to select external rom/ram that overlaps the bar and scr register locations, since this prevents potential bus contention. note in 8-bit system bus operation, imp accesses are not possible un- til the low byte of the bar is written. since the move.w instruc- tion writes the high byte followed by the low byte, this instruction guarantees the entire word is written. do not assign other devices on the system bus an address that falls within the address range of the peripherals defined by the bar. if this happens, an internal berr is generated to the core (if the address decode conflict enable (adce) bit is set) and the address decode conflict (adc) bit in the scr is set. 2.2.1 base address register the bar is a 16-bit, memory-mapped, read-write register consisting of the high address bits, the compare function code bit, and the function code bits. upon a total system reset, its value may be read as $bfff, but its value is not valid until written by the user. the address of this register is fixed at $0f2 in supervisor data space. bar cannot be accessed in user data space. bits 15?3?c2?c0 the fc2?c0 field is contained in bits 15?3 of the bar. these bits are used to set the address space of 4k-byte block of on-chip peripherals. the address compare logic uses these bits, dependent upon the cfc bit, to cause an address match within its address space. when the core is enabled, the function code bits will be driven by the core to indi- cate the type of cycle in process. in disable cpu mode, the fc pins are not present and are internally driven to 5. since, the user does not have any control over how the fc sig- nals are driven, it is recommended that the user write these bits to zero and write the cfc bit to zero to disable the fc comparison. note do not assign this field to the m68000 core interrupt acknowledge space (fc2?c0 = 7). cfc?ompare function code 0 = the fc bits in the bar are ignored. accesses to the imp 4k-byte block occur with- out comparing the fc bits. 1 = the fc bits in the bar are compared. the address space compare logic uses the fc bits to detect address matches. 15 13 12 11 0 fc2?c0 cfc base address 23 22 21 20 19 18 17 16 15 14 13 12
configuration, clocking, low power modes, and internal memory map motorola mc68lc302 reference manual 2-5 bits 11??ase address the high address field is contained in bit 11? of the bar. these bits are used to set the starting address of the dual-port ram. the address compare logic uses only the most sig- nificant bits to cause an address match within its block size. even though a23-20 are sig- nals are not available, they are driven internally by the core, or driven to zeroes in disable cpu mode or when halt has been asserted by an external master. 2.3 system configuration registers a number of entries in the m68000 exception vectors table (located in low ram) are reserved for the addresses of system configuration registers (see table 2-1). these regis- ters have seven addresses within $0f0-$0ff. the mc68lc302 uses one of the imp 32-bit reserved spaces for 3 registers added for the mc68lc302. these registers are used to con- trol the pll, clock generation and low power modes. see 2.4 clock generation and low power control. 2.4 clock generation and low power control the mc68lc302 includes a clock circuit that consists of crystal oscillator drive circuit capa- ble of driving either an external crystal or accepting an oscillator clock, a pll clock synthe- sizer capable of multiplying a low frequency clock or crystal such as a 32-khz watch crystal up to the maximum clock rate of each processor, and a low power divider which allows dynamic gear down and gear up of the system clock for each processor on the fly. on-chip clock synthesizers (with output system clocks) ?scillator drive circuits and pins ?ll clock synthesizer circuits with low power output clock divider block. low power control of imp ?low-go modes using pll clock divider blocks ?aried low power stop modes for optimizing wake-up time to low power mode power consumption: stand-by, doze and stop. 2.4.1 pll and oscillator changes to imp the oscillator that was on the mc68302 has been replaced by the new clock synthesizer described in this section.the registers related to the oscillator have been either removed or table 2-1. system configuration registers address name width description reset value $0f0 pitr 16 periodic interrupt timer register 0000 $0f2 bar 16 base address register bfff $0f4 scr 24 system control register 0000 0f $0f7 iwucr 8 imp wake-up control register 00 $0f8 iplcr 16 imp pll control register $0fa iomcr 8 imp operations mode control register 00 $0fb ipdr 8 imp power down register 00 $0fc res 32 reserved
configuration, clocking, low power modes, and internal memory map 2-6 mc68lc302 reference manual motorola changed according to the description below. several control bits are still available but have new locations. the low power modes on the mc68302 have changed completely and will be discussed later in 2.4.4.1 imp low power modes. 2.4.1.1 clock control register. the clock control register address $fa is not implemented on the mc68lc302. this register location has been reassigned to the iomcr and ickcr registers. the clock control register bits have been reassigned as follows: clko drive options (clkomod1?) these bits are now in the imp clock control register (iplcr) on the mc68lc302, see 2.4.3.4.2 imp pll and clock control register (iplcr). three-state tclk1 (tstclk1) this bit is now in the disc register on the mc68lc302, see 4.3.2 disable scc1 serial clocks out (disc). three-state rclk1 (tsrclk1) this bit is now in the disc register on the mc68lc302, see 4.3.2 disable scc1 serial clocks out (disc). disable brg1 (disbrg1) this bit has been removed since the brg1 pin was removed. 2.4.2 mc68lc302 system clock generation figure 2-3, the mc68lc302 system clock schematic, shows the imp clock synthesizer. the block includes an on-chip oscillator, a clock synthesizer, and a low-power divider, which allows a comprehensive set of options for generating the system clock. the choices offer many opportunities to save power and system cost, without sacrificing flexibility and control. in addition to performing frequency multiplication, the pll block can also provide extal to clko skew elimination, and dynamic low power divides of the output pll system clock. clock source and default settings are determined during the reset of the imp. the mc68lc302 decodes the modclk and vccsyn pins and the value of these pins deter- mines the initial clocking for the part. further changes to the clocking scheme can be made by software. after reset, the 68000 core can control the imp clocking through the following registers: 1. imp operation mode control register, iomcr (2.4.4.1.6 imp operation mode control register (iomcr)). 2. imp pll and clock control register, iplcr (2.4.3.4 frequency multiplication). 3. imp interrupt wake-up control register, iwucr (2.4.4.2.4 imp wake-up control register (iwucr)). 4. periodic interrupt timer register, pitr (see section 3 system integration block (sib) ).
configuration, clocking, low power modes, and internal memory map motorola mc68lc302 reference manual 2-7 2.4.2.1 default system clock generation. during the assertion of hardware reset, the value of the modclk and vccsyn input pins determine the initial pll settings according to table 2-2. after the deassertion of reset, these pins are ignored. the modclk and vccsyn pins control the imp clock selection at hardware reset. the imp pll can be enabled or disabled at reset only and the multiplication factor preset to support different industry standard crystals. after reset, the multiplication factor can be changed in the iplcr register, and the imp pll divide factor can be set in the iomcr register. note the imp input frequency ranges are limited to between 25 khz and the maximum operating frequency, and the pll output fre- quency range before the low power divider is limited to between 10 mhz and the maximum system clock frequency (25 mhz). note: by loading the iplcr register the user can change the multiplication factor of the pll after reset. by loading the iomcr register, the user can change the power saving divide factor of the imp pll. table 2-2. default system clock generation cselect vccsyn modclk example imp extal freq. imp pll imp mf+1 imp system clock 0 0x 25 mhz disabled x imp extal 0 10 4.192 mhz enabled 4 imp extalx4 0 11 32.768 khz enabled 401 imp extalx401 xtal extal imp pll imp system multiplication factor vco out imp (0 ?max pin pin brg mux (mf11?f0) divide factor (df3?f0) mux clk out divide by 2 mux clock osc. clkin pit clock figure 2-2. mc68lc302 pll clock generation schematic en fast wake up ringo clock mux operating freq)
configuration, clocking, low power modes, and internal memory map 2-8 mc68lc302 reference manual motorola note it is not possible to start the system with pll disabled and then enable the pll with software programming. 2.4.3 imp system clock generation 2.4.3.1 system clock configuration. the imp has an on-chip oscillator and phased locked loop (figure 2-2). these features provide flexible ways to save power and reduce system cost. the operation of the clock generation circuitry is determined by the fol- lowing registers. the imp operation mode control register, iomcr in 2.4.4.1.6 imp operation mode con- trol register (iomcr). the imp pll and clock control register, iplcr in a 32.768-khz watch crystal provides an inexpensive reference, but the extal reference crystal frequency can be any frequency from 25 khz to 6.0 mhz. additionally, the system clock frequency can be driven directly onto the extal pin. in this case, the extal frequency should be the exact system frequency desired (0 to maximum operating frequency) and the xtal pin should be left floating. fig- ure 2-4 shows all the external connections required for the on-chip oscillator (as well as the pll, vcc, and gnd connection . figure 2-2 shows the imp system clocks schematic with the imp pll enabled. figure 2-3 shows the imp system clocks schematic with the imp pll disabled. the clock generation features of the imp are discussed in the following paragraphs. 2.4.3.2 on-chip oscillator. a 32.768-khz watch crystal provides an inexpensive ref- erence, but the extal reference crystal frequency can be any frequency from 25 khz to 6.0 xtal extal imp system clock imp (0 ?mof*) pin pin * mof is maximum operating frequency figure 2-3. imp system clocks schematic - pll disabled brg divide by 2 mux clock osc. pit clock clkin
configuration, clocking, low power modes, and internal memory map motorola mc68lc302 reference manual 2-9 mhz. additionally, the system clock frequency can be driven directly onto the extal pin. in this case, the extal frequency should be the exact system frequency desired (0 to maxi- mum operating frequency) and the xtal pin should be left floating. figure 2-4 shows all the external connections required for the on-chip oscillator (as well as the pll, vcc, and gnd connection 2.4.3.3 phase-locked loop (pll). the imp pll? main function is frequency multipli- cation. the phase-locked loop takes the clkin frequency and outputs a high-frequency source used to derive the general system frequency of the imp. the imp pll is comprised of a phase detector, loop filter, voltage-controlled oscillator (vco), and multiplication block. 2.4.3.4 frequency multiplication. the imp pll can multiply the clkin input fre- quency by any integer between 1 and 4096. the multiplication factor may be changed to the desired value by writing the mf11?f0 bits in the iplcr. when the imp pll multiplier is modified in software, the imp pll will lose lock, and the clocking of the imp will stop until lock is regained (worst case is 2500 extal clocks). if an alteration in the system clock rate is desired without losing imp pll lock, the value in the low-power clock divider can be to modified to lower the system clock rate dynamically. the low power clock divider bits are located in the iomcr register. note if imp pll is enabled, the multiplication value must be large enough to result in the vco clock being greater than 10 mhz. figure 2-4. pll external components 20pf 330k 20m 20pf crystal extal xtal clock generation crystal oscillator clko vccsyn gndsyn 0.01 m f 0.1 m f ~390pf x mf xfc 0.1 m f vcc vcc iclvcc iclgnd
configuration, clocking, low power modes, and internal memory map 2-10 mc68lc302 reference manual motorola 2.4.3.4.1 low power pll clock divider. the output of the imp vco is sent to a low power divider block. the clock divider can divide the output frequency of the vco before it generates the system clock. the clock for the baud rate generators (brgs) bypasses this clock divider. the purpose of the clock divider is to allow the user to reduce and restore the operating fre- quency of the imp without losing the imp? pll lock. using the clock divider, the user can still obtain full imp operation, but at a slower frequency. the brg is not affected by the low power divider circuitry so previous brg divider settings will not have to be changed when the divide factors are changed. when the pll low power divider bits (df0?) are programmed to a non-zero value, the imp is in slow_go mode. the selection and speed of the slow_go mode may be changed at any time, with changes occurring immediately. note the imp low power clock divider is active only if the imp pll is active. the low-power divider block is controlled in the iomcr. the default state of the low-power divider is to divide all clocks by 1. if the low-power divider block is not used and the user is concerned that errant software could accidentally write the iomcr, the user may set a write protection bit in iomcr to pre- vent further writes to the register. 2.4.3.4.2 imp pll and clock control register (iplcr). iplcr is a 16-bit read/write reg- ister used to control the imp? pll, multiplication factor and clko drive strength. this reg- ister is mapped in the 68000 bus space at address $0f8. if the 68000 bus is set to 8 bits (busw grounded at reset), during 8-bit accesses, changes to the iplcr will take effect in the imp pll after loading the high byte of iplcr (the low byte is written first). the wp bit in iplcr is used as a protect mechanism to prevent erroneous writing. when this bit is set further accesses to the iplcr will be blocked. imp pll and clock control register (iplcr) $0f8 read/write 15 14 13 12 11 10 9 8 iplwp clkomod0? pen mf11 mf10 mf9 mf8 reset 0 0 0 vccsyn 0 0 0 vccsyn/modclk 76543210 mf7 mf6 mf5 mf4 m f 3 mf2 mf1 mf0 reset vccsyn/modclk1 0 0 vccsyn/modclk 0 0 modclk modclk
configuration, clocking, low power modes, and internal memory map motorola mc68lc302 reference manual 2-11 mf 11??ultiplication factor these bits define the multiplication factor that will be applied to the imp pll input frequen- cy. the multiplication factor can be any integer from 1 to 4096. the system frequency is ((mf bits + 1) x extal). the multiplication factor must be chosen to ensure that the re- sulting vco output frequency will be in the range from 10 mhz to the maximum allowed clock input frequency (e.g. 20 mhz for a 20 mhz imp). the value 000 results in a multiplier value of 1. the value $fff results in a multiplier value of 4096. any time a new value is written into the mf11?f0 bits, the imp pll will lose the lock condition, and after a delay of 2500 extal clocks, will relock. when the imp pll loses its lock condition, all the clocks that are generated by the imp pll are disabled. after hardware reset, the mf11?f0 bits default to either 0, 3 or 400 ($190 hex) depending on the modclk and vccsyn pins (giving a multiplication factor of 1, 4 or 401). if the mul- tiplication factor is 401, then a standard 32.768 khz crystal generates an initial general system clock of 13.14 mhz. if the multiplication factor is 4, then a standard 4.192 mhz crystal generates an initial general system clock of 16.768 mhz. the user would then write the mf bits or adjust the output frequency to the desired frequency. note since the clock source for the periodic interrupt timer is clkin (see figure 2-2), the pit timer is not disturbed when the imp pll is in the process of acquiring lock. pen?ll enable bit the pen bit indicates whether the imp pll is operating. this bit is written by the mc68lc302 based on the value of vccsyn during reset. when the imp pll is disabled, the vco is not operating in order to minimize power consumption. during hardware reset this bit is set if the vccsyn pin specifies that the imp pll is enabled. the only way to clear pen is to hold the vccsyn pin low during a hardware reset. 0 = the imp pll is disabled. clocks are derived directly from the extal pin. 1 = the imp pll is enabled. clocks are derived from the clkout output of the pll. clkodm0??lko drive mode 0? these bits control the output buffer strength of the clko pin. those bits can be dynami- cally changed without generating spikes on the clko pin. disabling clko will save pow- er and reduce noise. 00 = clock out enabled, full-strength output buffer. 01 = clock out enabled, 2/3-strength output buffer 10 = clock out enabled, 1/3-strength output buffer 11 = clock out disabled (clko is driven high by internal pullup) note these imp bits are in a different address location than in the mc68302, where they are located at address $fa (bits 15, 14).
configuration, clocking, low power modes, and internal memory map 2-12 mc68lc302 reference manual motorola iplwp?mp pll control write protect bit this bit prevents accidental writing into the iplcr. after reset, this bit defaults to zero to enable writing. setting this bit prevents further writing (excluding the first write that sets this bit). 2.4.3.5 imp internal clock signals. the following paragraphs describe the imp internal clock signals. 2.4.3.5.1 imp system clock. the imp system clock is supplied to all modules on the imp (with the exception of the brg clocks which are connected directly to the vco output with the pll enabled). the imp can be programmed to operate with or without imp pll. if imp pll is active, the system clock will be driven by pll clock divider output. if imp pll is not active, the system clock will be driven by the pll input clock (clkin). 2.4.3.5.2 brg clock. the clock to the brgs can be supplied from the imp pll input (clkin) when the imp pll is disabled, or from the imp pll vco output (when the pll is enabled). the brg prescaler input clock may be optionally programmed to be divided by 2 to allow very low baud rates to be generated from the system clock by setting the bcd bit in the iomcr. 2.4.3.5.3 pit clock. clkin is supplied to the periodic interrupt timer (pit) submodule which allows the pit clock to run independently of the system clock (refer to figure 2-2 and section 3 system integration block (sib)). 2.4.3.6 imp pll pins. the following pins are dedicated to the imp pll operation. 2.4.3.6.1 vccsyn. this pin is the v cc dedicated to the analog imp pll circuits. the volt- age should be well regulated, and the pin should be provided with an extremely low-imped- ance path to the v cc power rail if the pll is to be enabled. vccsyn should be bypassed to gndsyn by a 0.1- m f capacitor located as close as possible to the chip package. vccsyn should be tied to ground if the pll is to be disabled. 2.4.3.6.2 gndsyn. this pin is the gnd dedicated to the analog imp pll circuits. the pin should be provided with an extremely low-impedance path to ground. gdnsyn should be bypassed to vccsyn by a 0.1 m f capacitor located as close as possible to the chip pack- age. the user should also bypass gndsyn to vccsyn with a 0.01 m f capacitor as close as possible to the chip package. 2.4.3.6.3 xfc. this pin connects to the off-chip capacitor for the pll filter. one terminal of the capacitor is connected to xfc; the other terminal is connected to iqvcc. 2.4.3.6.4 modclk. modclk specifies what the initial vco frequency is after a hardware reset if vccsyn is tied high. during the assertion of reset, the value of the vccsyn and modclk input pins causes the pen bit and the mf11? bits of the imp pll and clock con- trol register (iplcr) $0f8 to be appropriately written.vccsyn and modclk also deter- mines if the oscillator? prescaler is used. after reset is negated, the modclk pins is ignored and becomes pa12. table 2-2 shows the combinations of vccsyn and modclk pins with the corresponding default settings.
configuration, clocking, low power modes, and internal memory map motorola mc68lc302 reference manual 2-13 2.4.4 imp power management the imp portion of the mc68lc302 has several low power modes from which to choose. 2.4.4.1 imp low power modes. the mc68lc302 provides a number of low power modes for the imp section. each of the operation modes has different current consumption, wake-up time, and functionality characteristics. the state of the imp? 68000 data and address bus lines can be either driven high, low or high impedance during low power stop mode by programming the low power drive control register (lpdcr). note for lowest current consumption, the sccs and brgs should be disabled before entering the low power modes. current con- sumption for all operating modes is specified in section 6 elec- trical characteristics. 2.4.4.1.1 stop mode. in stop mode, all parts of imp are inactive and the current con- sumption is less than 0.1ma. both the crystal oscillator and the imp pll are shut down. because both the oscillator and the pll must start up, the wake-up time takes 70000 extal clocks (for example, 70000 cycles of 32.768 khz crystal will take about 2.2 seconds). the stop mode is entered by executing the stop instruction with the lpm0? bits in the iomcr register set to 11. refer to 2.4.4.2.2 entering the stop/ doze/ stand_by mode for an example instruction sequence for use with the stop instruction. 2.4.4.1.2 doze mode. in doze mode, the oscillator is active in the imp but the imp pll is shut down. the current consumption depends on the frequency of the external crystal but is on the order of 500 m a. in doze mode, the imp is shut down. the wake-up time is 2500 cycles of the external crystal (for example, 2500 cycles of 32.768 khz crystal will take about 80 milliseconds.). doze mode has faster wake-up time than the stop mode, at the price of higher current consumption. the doze mode is entered by executing the stop instruction with the lpm1? bits in the iomcr register set to 10. refer to 2.4.4.2.2 entering the stop/ doze/ stand_by mode for an example instruction sequence for use with the stop instruction. 2.4.4.1.3 stand_by mode. in stand_by mode, the oscillator is active, and the imp pll, if enabled, is active but the imp clock is not active and the imp is shut down. current con- table 2-3. imp low power modes - imp pll enabled operation mode oscillator pll imp clock wake_up (osc. clock cycles) current consumption (approximate) method of entry/ lpm bits imp functionality stop not active not active not active 70000 osc. clocks <0.1ma stop instruction/ lpm1?=11 no doze active not active not active 2500 osc clocks about 500ua stop instruction/ lpm1?=10 no stand_by active active (if enabled not active 2? system clock cycles about 5ma stop instruction/ lpm1?=01 partial (brg clock is active) slow_go/ normal active active (if enabled) active low, depends on clk freq. write to df3? full
configuration, clocking, low power modes, and internal memory map 2-14 mc68lc302 reference manual motorola sumption in stand-by mode is less than less than 5ma. the wake up time is a few imp system clock cycles. the stand_by mode is entered by executing the stop instruction with the lpm1? bits in the iomcr register set to 01. refer to 2.4.4.2.2 entering the stop/ doze/ stand_by mode for an example instruction sequence for use with the stop instruction. 2.4.4.1.4 slow_go mode. in the slow-go mode, the imp is fully operational but the imp pll divider has been programmed with a value that is dividing the imp pll vco output to the system clock in order to save power. the pll output divider can only be used with the imp pll enabled. the divider value is programmed in the df3? bits in the iomcr. the clock may be divided by a power of 2 (2 0 ?2 15 ). no functionality is lost in slow-go mode. 2.4.4.1.5 normal mode. in normal mode the imp part is fully operational and the sys- tem clock from the pll is not being divided down. 2.4.4.1.6 imp operation mode control register (iomcr). iomcr is a 8-bit read/ write register used to control the operation modes of the imp. the wp bit in iomcr is used as a protect mechanism to prevent erroneous writing of iomcr. iomcr $0fa read/write iomwp?mp operation mode control write protect bit this bit prevents accidental writing into the iomcr. after reset, this bit defaults to zero to enable writing. setting this bit prevents further writing (excluding the first write that sets this bit). df 3??ivide factor the divide factor bits define the divide factor of the low power divider of the pll. these bits specify a divide range between 2 0 and 2 15 . changing the value of these bits will not cause a loss of lock condition to the imp pll. bcd?rg clock divide control this bit controls whether the divide-by-two block shown in figure 2-2 is enabled. 0 = the brg clock is divided by 1. 1 = the brg clock is divided by 2. 76543210 iomwp df3 df2 df1 d f 0 bcd lpm1 lpm0 reset: 0 0000000
configuration, clocking, low power modes, and internal memory map motorola mc68lc302 reference manual 2-15 lpm?ow power modes when the 68000 core executes the stop instruction, the imp will enter the specified mode. lpm1?: 00 = normal - the imp pll and clock oscillator will continue to operate normally. 01 = stand_by mode 10 = doze mode 11 = stop mode 2.4.4.1.7 low power drive control register (lpdcr). this register controls the state of the imp? 68000 address and data buses during the standby, doze, and stop modes. by programming this register it is possible to minimize power consumption due to external pul- lups or pull downs, or floating inputs. lpdcr bar+$82a read/write lpden?ow power drive enable 0 - the imp 68000 data and address buses will be high impedance. 1 - the imp 68000 data and address buses to be driven according to the lpdl bit. lpdl?ow power drive data low 0 - the data bus will be driven high when the lpden bit is set. 1 - the data bus will be driven low when the lpden bit is set. lpal-low power drive address low 0 - the address bus will be driven high when the lpden bit is set. 1 - the address bus will be driven low when the lpden bit is set. 2.4.4.1.8 imp power down register (ipwrd). the ipwrd is a 8-bit read/ write register located at $0fb that is used to control the low power operation of the imp. this register must be written with the same operand as the stop instruction that follows. this tells the hard- ware what level of interrupt (and above) will stop the mc68lc302 from entering low power if it occurs while the clocks are being stopped. 2.4.4.1.9 default operation modes, see 2.4.2.1 default system clock generation. 2.4.4.2 low power support. the following sections describe how to enter the various low power modes. 2.4.4.2.1 enter the slow_go mode. when the required imp performance can be achieved with a lower clock rate, the user can reduce power consumption by dividing imp 76543210 l pa l lpdl lpden reset: 0 0000000
configuration, clocking, low power modes, and internal memory map 2-16 mc68lc302 reference manual motorola pll output clock that provides the imp system clock. switching between the normal and slow_go modes is achieved by changing the df3? field in the iomcr register to a non- zero value. the imp pll will not lose lock when the df3? field in the iomcr register is changed. 2.4.4.2.2 entering the stop/ doze/ stand_by mode. entering the stop/ doze/ stand_by mode is achieved by the 68000 core executing the following code: this code is position independent. the core must be in the supervisor state to execute the stop instruction, therefore the write to $000000fb must be done in the supervisor state (function code 5, supervisor data). the core trace exception should be disabled, otherwise the low power control will not enter the stop mode. to guarantee supervisor state and trace exceptions disabled, this code should be part of a trap routine. upon entering the trap routine, examine the stacked status register. if it indi- cates the supervisor state, then execute this code to enter stop mode. if not supervisor, do not execute this code (could perform some application-specific error): note the ri/pb9, dte/pb10, and periodic interrupt timer timeout in- terrupts conditions will generate level 4 interrupts. the user should set the 68000 interrupt mask register to the appropriate level before executing this code. imp? low power control logic will: 1. detect the write cycle. 2. check if bit 5 = 1 (supervisor space) (if it is 0, the low power request will be ignored). 3. sample the interrupt mask bits (bits 0?). if during this process of stopping the clocks nop move.b *+6(pc),$000000fb ;copy stop operand high byte to addr 000000fb stop #$xxxx ;xxxx -> sr nop trap_x btst.b #5,(sp) ; supervisor? beq.s no_stop nop ; flush execution, bus pipes move.b *+6(pc),$000000fb ;copy stop operand high byte to addr 000000fb stop #$xxxx ; xxxx -> sr nop rte no_stop ... ; error routine?
configuration, clocking, low power modes, and internal memory map motorola mc68lc302 reference manual 2-17 an interrupt of higher level than the mask is asserted to the core, this process will abort. 4. wait for 16 clocks to guarantee the execution of the stop command by the core. bg and bgack will reset the 16-clock counter and it will restart its count. 5. assert bus request signal to the core. 6. wait for bus grant from the core 7. force the imp to the selected power-down mode, as defined in table 2-3. 2.4.4.2.3 imp wake-up from low power stop modes. the imp can wake up from stop/doze/stand_by mode to normal/slow_go mode in response to inputs from the following sources: 1. asserting both reset and halt (hard reset) pins. 2. asserting (high to low transition) either pb9 or pb10 pins (if these interrupts are en- abled). 3. a timeout of the periodic interrupt timer (if the pit interrupt is enabled). when one of these events occur (and the corresponding event bit is set), the imp low power controller will asynchronously restart the imp clocks. then imp low power control logic will release the 68000 bus and the imp will return to normal operation. if one of the above wake- up events occurs during the execution of the stop command, the low power control logic will abort the power down sequence and return to normal operation. note the ri/pb9, dte/pb10, and periodic interrupt timer timeout in- terrupts conditions will generate level 4 interrupts.the user should also set the 68000 interrupt mask in the status register (sr) to the appropriate level before executing the stop com- mand to ensure that the imp will wake up to the desired events. 2.4.4.2.4 imp wake-up control register (iwucr). the iwucr contains control for the wake-up options. this register can be read and written by the 68000 core. iwucr $0f7 read/write pb9ev?b9 event this bit will be set to one when there is a high to low transition on the pb9 pin. when pb9en is set and pb9ev is set, the imp will wake-up from the selected power down state, and a pb9 interrupt will be generated. the imp cannot enter the power-down mode if 7 6 5 4 3 2 1 0 0 pite pb10e pb9ev 0 piten pb10en pb9en reset: 0 0 0 0 0 0 0 0
configuration, clocking, low power modes, and internal memory map 2-18 mc68lc302 reference manual motorola pb9ev and pb9en are both set to one. pb9ev is cleared by writing a one (writing a zero has no effect). in modem applications ri should be connected to the pb9 pin. pb10ev?b10 event this bit will be set to one when there is a high to low transition on the pb10 pin. when pb10en is set and pb10ev is set, the imp will wake-up from the selected power down state, and the pb10 interrupt will be generated. the imp cannot enter the power-down mode when pb10ev and pb10en are both set to one. pb10ev is cleared by writing a one (writing a zero has no effect). in modem applications the dte txd line may be connected to the pb10 pin. pitev?it event this bit will be set to one when there is a time-out on the periodic interrupt timer (pit). when piten bit is set and a time-out occurs (pitev is set), the imp will wake-up from the selected power down, and a pit interrupt will be generated. the imp cannot enter the power-down mode if pitev and piten are both set to one. pitev is cleared by writing a one (writing a zero has no effect). pb9en?b9 enable this bit, when set, enables the imp to wake up from power down mode and generate an interrupt when the pb9 event bit becomes set. pb10en?b10 enable this bit, when set, enables the imp to wake up from power down mode and generate an interrupt when the pb10 event bit becomes set. piten?it enable this bit, when set, enables the imp to wake up from power down mode and generate an interrupt when the pit event bit becomes set, see 3.7.4 periodic interrupt timer (pit). 2.4.4.3 fast wake-up in a system clocked with a 32-khz oscillator, the wake-up recovery time from doze and stop modes may be too long for some applications. in order to shorten this time, an internal ring oscillator (called ringo) can clock the chip (the term ?eal clock?in the following discussion refers to the clock whose source is the external oscillator or crystal; the pll can be either enabled or disabled). one reason for using the fast wake-up is: to allow logic to operate in the time frame between the wake-up command and the ac- tual real clock recovery (from the external crystal or oscillator). note if the sccs use the internal clock, or if they use external clock and the ringo/external frequency ratio does not comply with the 1 / 2.5 maximum ration specification, then they cannot be en- abled until the real clock has resumed operation.
configuration, clocking, low power modes, and internal memory map motorola mc68lc302 reference manual 2-19 the criteria for enabling ringo and waking up the cpu (by giving it an interrupt) is: rin- goen=1 and an unmasked pitev, pb10ev, or pb9ev event occurs (please refer to the iwucr register) the internal ring oscillator is not enabled if the pll is disabled. a system with the pll dis- abled has to have an external oscillator connected in order to shorten the wake-up time. there are two possible interrupts to the cpu from the ringo logic: ?interrupt when ringo is enabled; the cpu is always interrupted when ringo starts oscillating (ringoen bit enables both ring oscillator and enables the interrupt to the cpu). event bits for this interrupt are all wake-up events. ?maskable interrupt when the system clock switches to the real clock. the event bit for this interrupt is in the ring oscillator event register. the ringo interrupts can be either at level 1, 6, or 7 according to ricr bits. if the cpu de- termines that the system needs the real clock, it programs the reclmode bits which en- ables the oscillator and pll and interrupts if necessary; if it decides that the system can go back to sleep, it executes the normal power-down sequence which turns off ringo. upon switching to the real clock, the cpu can be interrupted by programming the ricr bits. (note that ringo is turned off either at the end of a power down sequence, or when the pll has gained lock). if the reclmode bits are programmed to enable the pll and the oscillator, the user is allowed to enter low power mode after the real clock has resumed. the chip will not operate correctly if the cpu enters the low power sequence while the pll is waking up. resetting of the ringoen bit is allowed only if the system is clocked by the real clock. the clko signal can be disabled by software if the user cannot operate the system at the ringo frequency. 2.4.4.3.5 ring oscillator control register (ringocr) ringocr bar+$81a read/write ringoen ?ring oscillator enable 0 = ring oscillator is not used 1 = ring oscillator is enabled reclmode ?real clock mode 00 = do not enable the real clock 01 = enable the real clock and switch the system clock from ringo to the real clock once it is stable 10 = enable the real clock and generate an interrupt to the cpu after the switch occurs 11 = reserved 76543210 ricr reclmode ringoen reset: 0 0000000
configuration, clocking, low power modes, and internal memory map 2-20 mc68lc302 reference manual motorola ricr ?ring oscillator interrupt control 00 = connect ringo interrupts to 68k interrupt request level 1 01 = connect ringo interrupts to 68k interrupt request level 6 10 = connect ringo interrupts to 68k interrupt request level 7 11 = reserved 2.4.4.3.6 ring oscillator event register (ringoevr). ringoevr bar+$81b read/write reclsev ?real clock switch event 0 = event has not occurred 1 = real clock is now the system clock (this bit is reset by writing 1) bits 7-1 ?reserved 2.5 mc68lc302 dual port ram the internal 1152-byte dual-port ram has 576 bytes of system ram (see table 2-4) and 576 bytes of parameter ram (see table 2-5). the parameter ram contains the buffer descriptors for each of the two scc channels, the scp, and the two smc channels. the memory structures of the three scc channels are identical. when any scc, scp, or smc channel buffer descriptors or parameters are not used, their parameter ram area can be used for additional memory. for detailed informa- tion about the use of the buffer descriptors and protocol parameters in a specific protocol, see section 4 communications processor (cp). cp. base + 67e contains the mc68lc302 revision number. 76543210 reserved reclsev reset: 0 0000000 table 2-4. system ram address width block description base + 000 base + 23f 576 bytes ram user data memory base +240 base + 3ff reserved (not implemented)
configuration, clocking, low power modes, and internal memory map motorola mc68lc302 reference manual 2-21 # modi?d by the cp after a cp or system reset. table 2-5. parameter ram address width block description base + 400 base + 408 base + 410 base + 418 base + 420 base + 428 base + 430 base + 438 base + 440 base + 448 base + 450 base + 458 base + 460 base + 468 base + 470 base + 478 4 word 4 word 4 word 4 word 4 word 4 word 4 word 4 word 4 word 4 word 4 word 4 word 4 word 4 word 4 word 4 word scc1 scc1 scc1 scc1 scc1 scc1 scc1 scc1 scc1 scc1 scc1 scc1 scc1 scc1 scc1 scc1 rx bd 0 rx bd 1 rx bd 2 rx bd 3 rx bd 4 rx bd 5 rx bd 6 rx bd 7 tx bd 0 tx bd 1 tx bd 2 tx bd 3 tx bd 4 tx bd 5 tx bd 6 tx bd 7 base + 480 base + 4bf scc1 scc1 specific protocol parameters base + 4c0 base + 4ff reserved (not implemented) base + 500 base + 508 base + 510 base + 518 base + 520 base + 528 base + 530 base + 538 base + 540 base + 548 base + 550 base + 558 base + 560 base + 568 base + 570 base + 578 4 word 4 word 4 word 4 word 4 word 4 word 4 word 4 word 4 word 4 word 4 word 4 word 4 word 4 word 4 word 4 word scc2 scc2 scc2 scc2 scc2 scc2 scc2 scc2 scc2 scc2 scc2 scc2 scc2 scc2 scc2 scc2 rx bd 0 rx bd 1 rx bd 2 rx bd 3 rx bd 4 rx bd 5 rx bd 6 rx bd 7 tx bd 0 tx bd 1 tx bd 2 tx bd 3 tx bd 4 tx bd 5 tx bd 6/dram refresh tx bd 7/dram refresh base + 580 base + 5bf scc2 scc2 specific protocol parameters base + 5c0 base + 5ff reserved (not implemented) base + 600 base + 65f 48 words not used by cp (available to user) base + 660 base + 666 base + 668 base + 66a base + 66c base + 66e # base + 67a base + 67c base + 67e # 3 word word word word word 6 word word word word smc smc1 smc1 smc2 smc2 smc1?mc2 scp scc1?cc3 cp reserved rx bd tx bd rx bd tx bd internal use rx/tx bd berr channel number mc68pm302 revision number base + 680 base + 6bf reserved base + 6c0 base + 7ff reserved (not implemented)
configuration, clocking, low power modes, and internal memory map 2-22 mc68lc302 reference manual motorola in addition to the internal dual-port ram, a number of internal registers support the functions of the various m68000 core peripherals. the internal registers (see table 2-6) are memory- mapped registers offset from the bar pointer and are located on the internal m68000 bus. note all undefined and reserved bits within registers and parameter ram values written by the user in a given application should be written with zero to allow for future enhancements to the device.
configuration, clocking, low power modes, and internal memory map motorola mc68lc302 reference manual 2-23 2.6 internal registers map table 2-6. internal registers map address name width block description reset value base + 800 res 16 idma reserved base + 802 cmr 16 idma channel mode register 0000 0000 base + 804 sapr 32 idma source address pointer xxxx xxxx base + 808 dapr 32 idma destination address pointer xxxx base + 80c bcr 16 idma byte count register 00 base + 80e * csr 8 idma channel status register base + 80f res 8 idma reserved base + 810 fcr 8 idma function code register xx base + 811 res 8 idma reserved base + 812 # gimr 16 int cont global interrupt mode register 0000 base + 814 * ipr 16 int cont interrupt pending register 0000 base + 816 imr 16 int cont interrupt mask register 0000 base + 818 * isr 16 int cont in-service register 0000 base + 81a ringocr 8 int cont ring oscillator control register 00 base + 81b ringoevr 8 int cont ring oscillator event register 00 base + 81c res 16 int cont reserved base + 81e # pacnt 16 pio port a control register 0000 base + 820 # paddr 16 pio port a data direction register 0000 base + 822 # padat 16 pio port a data register xxxx ## base + 824 # pbcnt 16 pio port b control register 0080 base + 826 # pbddr 16 pio port b data direction register 0000 base + 828 # pbdat 16 pio port b data register xxxx ## base + 82a lpdcr 8 pio low power drive control register 00 base + 82c bsr 8 cs bus switch register 0000 base + 82e res 16 cs reserved base + 830 # br0 16 cs0 base register 0 c001 base + 832 # or0 16 cs0 option register 0 dffd base + 834 # br1 16 cs1 base register 1 c000 base + 836 # or1 16 cs1 option register 1 dffd base + 838 # br2 16 cs2 base register 2 c000 base + 83a # or2 16 cs2 option register 2 dffd base + 83c # br3 16 cs3 base register 3 c000 base + 83e # or3 16 cs3 option register 3 dffd base + 840 tmr1 16 timer timer unit 1 mode register 0000 base + 842 trr1 16 timer timer unit 1 reference register ffff base + 844 tcr1 16 timer timer unit 1 capture register 0000 base + 846 tcn1 16 timer timer unit 1 counter 0000 base + 848 res 8 timer reserved base + 849 * ter1 8 timer timer unit 1 event register 00 base + 84a wrr 16 wd watchdog reference register ffff base + 84c wcn 16 wd watchdog counter 0000 base + 84e res 16 timer reserved base + 850 tmr2 16 timer timer unit 2 mode register 0000 base + 852 trr2 16 timer timer unit 2 reference register ffff base + 854 tcr2 16 timer timer unit 2 capture register 0000 base + 856 tcn2 16 timer timer unit 2 counter 0000 base + 858 res 8 timer reserved
configuration, clocking, low power modes, and internal memory map 2-24 mc68lc302 reference manual motorola # reset only upon total system reset. (reset and halt assert together), but not on the execution of an m68000 reset instruction. see the reset pin description for details. ## the output latches are unde?ed at total system reset. * event register with special properties. base + 859 * ter2 8 timer timer unit 2 event register 00 base + 85a res 16 timer reserved base + 85c res 16 timer reserved base + 85e res 16 timer reserved base + 860 cr 8 cp command register 00 base + 861 reserved base + 87f base + 880 res 16 scc1 reserved base + 882 scon1 16 scc1 scc1 configuration register 0004 base + 884 scm1 16 scc1 scc1 mode register 0000 base + 886 dsr1 16 scc1 scc1 data sync. register 7e7e base + 888 * scce1 8 scc1 scc1 event register 00 base + 889 res 8 scc1 reserved base + 88a sccm1 8 scc1 scc1 mask register 00 base + 88b res 8 scc1 reserved base + 88c sccs1 8 scc1 scc1 status register 00 base + 88d res 8 scc1 reserved base + 88e res 16 scc1 reserved base + 890 res 16 scc2 reserved base + 892 scon2 16 scc2 scc2 configuration register 0004 base + 894 scm2 16 scc2 scc2 mode register 0000 base + 896 dsr2 16 scc2 scc2 data sync. register 7e7e base + 898 * scce2 16 scc2 scc2 event register 0000 base + 899 res 8 scc2 reserved base + 89a sccm2 8 scc2 scc2 mask register 00 base + 89b res 8 scc2 reserved base + 89c sccs2 8 scc2 scc2 0000 base + 89d res 8 scc2 reserved base + 89e res 16 scc2 reserved base + 8a0 reserved base + 8ae base + 8b0 spmode 16 scm scp, smc mode and clock control register 0000 base + 8b2 # simask 16 si serial interface mask register ffff base + 8b4 # simode 16 si serial interface mode register 0000 base + 8b6 reserved base +8da base + 8dc # pndnr 8 pio pin io data direction register 0000 base + 8de # pndat 8 pio pin io data register 0000 base + 8e0 reserved base +8ec base + 8ee # disc 16 sib disable scc1 serial clocks 0000 base + 8f0 reserved base + fff table 2-6. internal registers map address name width block description reset value
motorola mc68lc302 reference manual 3-1 section 3 system integration block (sib) the mc68lc302 contains an extensive sib that simplifies the job of both the hardware and software designer. most of the features are taken from the mc68302 without change, fea- tures that have been added are highlighted in bold text. note this section will only present the register descriptions for each block. for more information on the operation of each block, please refer to the mc68302 users?manual . items that are new or have changed will be described in detail. the sib includes the following functions: idma controller interrupt controller with two modes of operation parallel input/output (i/o) ports, some with interrupt capability parallel input/output ports on d15-d8 in 8 bit mode on-chip 1152-byte dual-port ram four timers including a watchdog timer and periodic interrupt timer four programmable chip-select lines with wait-state generator logic glueless interface to sram, eprom, flash eprom, and eeprom system control ?ystem status and control logic ?isable cpu logic (m68000) ?us arbitration logic with low-interrupt latency support (for internal dma) ?ardware watchdog for monitoring bus activity ?ram refresh controller ?rogrammable bus width boot from scc 3.1 system control the imp system functions are configured using the system control register (scr). the fol- lowing systems are configurated: system status and control logic
system integration block (sib) 3-2 mc68lc302 reference manual motorola ?s control during read-modify-write-cycles disable cpu (m68000) logic bus arbitration logic with low-interrupt latency support (disable cpu only) hardware watchdog low-power (standby) modes freeze control (only supported in the pga package) 3.1.1 system control register (scr) the scr is a 32-bit register that consists of system status, control bits, a bus arbiter control bit, and hardware watchdog control bits. refer to figure 3-1 and to the following paragraphs for a description of each bit in this register. the scr is a memory-mapped read-write regis- ter. the address of this register is fixed at $0f4 in supervisor data space (fc = 5). $f4 $f5 $f6 figure 3-1. system control register 31 30 29 28 27 26 25 24 res 0 0 0 i ipa hwt wpv adc 23 22 21 20 19 18 17 16 rme erre vge wpve rmcst emws adce bclm 15 14 13 12 11 10 9 8 frzw frz2 frz1 sam hwden hwdcn2?wdcn0 table 3-1. scr register bits bit name ipa interrupt priority active hwt hardware watchdog timeout wpv write protect violation adc address decode conflict rme ram microcode enable erre external risc request enable vge vector generation enable wpve write protect violation enable rmcst read-modify-write cycle special treatment emws external master wait state adce address decode conflict enable bclm bus clear mask frzw freeze watch dog timer enable frz1 freeze timer 1 enable frz2 freeze timer 2 enable sam synchronous access mode hwden hardware watchdog enable hwdcn hardware watchdog count
system integration block (sib) motorola mc68lc302 reference manual 3-3 3.1.2 system status bits bits 27-24 of the scr are used to report events recognized by the system control logic. on recognition of an event, this logic sets the corresponding bit in the scr. these bits may be read at any time. a bit is reset by a one and is left unchanged by a zero. more than one bit may be reset at a time. for more information on these bits, please refer to the mc68302 user?s manual . after system reset (simultaneous assertion of reset and halt ), these bits are cleared. ipa?nterrupt priority active this bit is set when the m68000 core has an unmasked interrupt request. note if bclm is set, an interrupt handler will normally clear ipa at the end of the interrupt routine to allow an alternate bus master to regain the bus; however, if bclm is cleared, no additional action needs to be taken in the interrupt handler. hwt?ardware watchdog timeout this bit is set when the hardware watchdog (see 3.1.5 hardware watchdog) reaches the end of its time interval; an internal berr is generated following the watchdog timeout, even if this bit is already set. wpv?rite protect violation this bit is set when a bus master attempts to write to a location that has rw set to zero (read only) in its associated base register (br3?r0). adc?ddress decode conflict this bit is set when a conflict has occurred in the chip-select logic because two or more chip-select lines attempt assertion in the same bus cycle. 3.1.3 system control bits the system control logic uses six control bits in the scr. wpve?rite protect violation enable 0 = an internal berr is not asserted when a write protect violation occurs. 1 = an internal berr is asserted when a write protect violation occurs. after system reset, this bit defaults to zero. note wpv will be set regardless of the value of wpve. rmcst?mc cycle special treatment 0 = the locked read-modify-write cycles of the tas instruction will be identical to the m68000 (as and cs will be asserted during the entire cycle). the arbiter will issue
system integration block (sib) 3-4 mc68lc302 reference manual motorola bg , regardless of the m68000 core rmc . if an imp chip select is used then the dtack generator will insert wait states on the read cycle only. 1 = the imp uses the internal rmc to negate as and cs at the end of the read portion of the rmc cycle and reasserts as and cs at the beginning of the write portion. bg will not be asserted until the end of the write portion. if an imp chip select is used, the dtack generator will insert wait states on both the read and write portion of the cycles. the assertion of the internal rmc by the m68000 core is seen by the arbiter and will pre- vent the arbiter from issuing bus grants until the completion of m68000-initiated locked read-modify-write activity. after system reset, this bit defaults to zero. emws?xternal master wait state (emws) (valid only in disable cpu mode) when emws is set and an external master is using the chip-select logic for dtack gen- eration or is synchronously reading from the internal peripherals (sam = 1), one additional wait state will be inserted in every memory cycle to external memory, peripherals, and al- so, in every cycle to internal memory and peripherals. when emws is cleared, all syn- chronous internal accesses will be with zero wait states and the chip-select logic will generate dtack after the exact programmed number of wait states. the chip-select lines are asserted slightly earlier for internal master memory cycles than for an external master. emws should be set whenever these timing differences will necessitate an additional wait state for external masters. after system reset, this bit defaults to zero. adce?ddress decode conflict enable 0 = an internal berr is not asserted by a conflict in the chip-select logic when two or more chip-select lines are programmed to overlap the same area. 1 = an internal berr is asserted by a conflict in the chip-select logic when two or more chip-select lines are programmed to overlap the same area. bclm?us clear mask 0 = the arbiter does not use the m68000 core internal ipend signal to assert the in- ternal bus clear signals. 1 = the arbiter uses the m68000 core internal ipend signal to assert the internal bus clear signals. sam?ynchronous access mode (valid only in disable cpu mode) this bit controls how external masters may access the imp peripheral area. this bit is not relevant for applications that do not have external bus masters that access the imp. in ap- plications such as disable cpu mode, in which the m68000 core is not operating, the user should note that sam may be changed by an external master on the first access of the imp, but that first write access must be asynchronous with three wait states. (if dtack is used to terminate bus cycles, this change need not influence hardware.) 0 = asynchronous accesses. all accesses to the imp internal ram and registers (in- cluding bar and scr) by an external master are asynchronous to the imp clock. read and write accesses are with three wait states, and dtack is asserted by the imp assuming three wait-state accesses. this is the default value.
system integration block (sib) motorola mc68lc302 reference manual 3-5 1 = synchronous accesses. all accesses to the imp internal ram and registers (in- cluding bar and scr) must be synchronous to the imp clock. synchronous read accesses may occur with one wait state if emws is also set to one. rme?am microcode enable this bit is used to initiate the execution of communication processor microcode that has been loaded into the dual port ram. see appendix c in mc68302um/ad. vge?ector generation enable (not supported by the mc68lc302) this bit must be written to zero. since the mc68lc302 cannot decode an interrupt ac- knowledge cycle from an external processor without the fc pins, the user should provide either an autovector signal or a vector back to the host processor during an interrupt ac- knowledge cycle for the mc68lc302. the user should then read the ipr to determine which the interrupt source. 3.1.4 freeze control used to freeze the activity of selected peripherals, frz is useful for system debugging pur- poses (for more information on these bits, please refer to the mc68302 users?manual) : frz1 ?freeze timer 1 enable 0 = freeze timer 1 logic is disabled 1= freeze timer 1 logic is enabled after system reset this bit defaults to zero. frz2 ?freeze timer 2 enable 0 = freeze timer 2 logic is disabled 1= freeze timer 2 logic is enabled after system reset this bit defaults to zero. frzw ?freeze watchdog timer enable 0 = freeze watchdog timer logic is disabled 1= freeze watchdog timer logic is enabled after system reset this bit defaults to zero. 3.1.5 hardware watchdog the hardware watchdog logic is used to assert an internal berr and set hwt when a bus cycle is not terminated by dtack and after a programmable number of clock cycles has elapsed. the hardware watchdog logic uses four bits in the scr. hwden?ardware watchdog enable 0 = the hardware watchdog is disabled. 1 = the hardware watchdog is enabled. after system reset, this bit defaults to one to enable the hardware watchdog.
system integration block (sib) 3-6 mc68lc302 reference manual motorola hwdcn?wdcn0?ardware watchdog count 2? 000 = an internal berr is asserted after 128 clock cycles (8 m s, 16-mhz clock) 001 = an internal berr is asserted after 256 clock cycles (16 m s, 16-mhz clock) 010 = an internal berr is asserted after 512 clock cycles (32 m s, 16-mhz clock) 011 = an internal berr is asserted after 1k clock cycles (64 m s, 16-mhz clock) 100 = an internal berr is asserted after 2k clock cycles (128 m s, 16-mhz clock) 101 = an internal berr is asserted after 4k clock cycles (256 m s, 16-mhz clock) 110 = an internal berr is asserted after 8k clock cycles (512 m s, 16-mhz clock) 111 = an internal berr is asserted after 16k clock cycles (1 ms, 16-mhz clock) 3.2 programmable data bus size switch the following procedure allows 68lc302 to be booted in an 8 or 16 bit bus width and then switched to 16 or 8 bit bus width for future accesses. it does not implement true dynamic bus sizing, but allows a software reconfiguration of the busw pin. 3.2.1 bus switch register (bsr) bsr base +$82c bwsen - bus width switch enable when this bit is toggled from a zero to a one, the bus width switch mechanism is enabled. from the point this bit is toggled, the bus width is determined by the bsw bit of this reg- ister. if another bus width switch is necessary, this bit must be toggled back to zero and then one again. setting this bit implements a hardware state machine that arbitrates the internal bus away from the 302 core, changes the busw pin internally, and then gives the bus back to the 302 core. busw - bus width this bit determines the bus width after the bus width switch is performed. 0 - data bus width is 8 bits 1 - data bus width is 16 bits. 3.2.2 basic procedure: the mc68lc302 is booted in its 8-bit mode by externally connecting the busw pin to gnd. it is expected that the mc68lc302 will be executing out of eprom or flash at this time, and that no external data memory is available in 8-bit mode. the mc68lc302 initializes the bar register to place the 4k block of dual-port ram and peripherals in an area that does not overlap the eprom region. note that this is part of a normal 302 initialization sequence. also note that the cfc bit of the bar register should not be set -- it must be cleared. 7 6 5 4 3-0 0 bsw bswen 0 0 0 0 0 0 0
system integration block (sib) motorola mc68lc302 reference manual 3-7 at this time other desired initialization should be completed on the mc68lc302. no bus masters (idma, sdma, or external) should be enabled. while in 8-bit mode, the mc68lc302 should initialize the external memory registers that control the16-bit external memory space. external memory refresh is not enabled at this time, but all other desired external memory control features should be enabled. note that the mc68lc302 does not access the external memory itself yet, only the external memory control registers. the 302-based device now copies a special boot code to the user area of the internal dual- port ram of the 302, and then jumps to the start of that code. this code is copied as ?ata to the dual-port ram. to summarize, the procedure is then: boot up 302-derivative perform required 8 bit operations write code to the dual port ram for the bus width change jump to code in the dual port ram when ready to use 16-bit bus width, set the busw bit to 1 toggle the bwsen bit from zero to one. allow time for bus arbitration and the instruction pipeline to clear initialize external memory copy boot code from eprom to external memory space execute code from external memory space note the stack which is shared by both codes should be placed in the dual ported ram. copy the stack to dual port ram after switch- ing to the second ram and change the stack pointer. 3.3 load boot code from an scc the mc68lc302 provides the capability of downloading program code into scc1 and beginning program execution in the dual port ram. the boot function has two clocking options: external and internal. in the first mode, the user provides the chip with an external clock 16* the desired baud rate. in the second mode, the risc processor programs the scc into uart mode running at approximately 9600 baud (assuming the frequency of the clock to the chip has one of two nominal values 32.768 khz or 4.192 mhz). the first 576 bytes that are received into scc1 are stored in the dual-port ram. no error checking is performed on the incoming serial bit stream. the 68000 processor then begins
system integration block (sib) 3-8 mc68lc302 reference manual motorola executing from the first location of the dual-port ram to complete the boot process. this function is not supported for scc2. three pins are sampled to determine the mode of operation and clock of the boot function: pa7?ampled during hard reset (reset and halt asserted) 0 boot from scc is enabled 1 boot from scc is disabled pa5?ampled within 100 clocks from the negation of reset 0 internal clock 1 external clock 16* the bit rate on tclk1 and rclk1 pa12 (modclk0) sampled during hard reset (reset and halt asserted) 0 nominal input frequency on extal is 4.192 mhz 1 nominal input frequency on extal is 32.768 khz to enable the boot function, the pa7 pin must be pulled low during system reset. (system reset is defined by the reset and halt pins being asserted.) the pa7 pin must be pulled high during system reset, if boot mode is not to be enabled. once the mc68lc302 detects that the pa7 pin is asserted, it internally keeps the halt signal to the 68k core asserted after system reset is complete. this action prevents the 68000 from fetching the reset vec- tor. note pa7 needs to be either pulled up or pulled down. do not leave this pin floating during reset. once system reset is complete, the risc processor programs the bar register to $0000 to place the dual-port ram at the low end of system memory. it then samples the pa5 pin to determine the clock source for the uart. note pa5 is expected to be valid for 100 clocks after the negation of reset . if pa5 is pulled high, scc1 is programmed for external clocks. in this mode, the user has to connect an external clock 16* the bit rate to tclk1 and rclk1. if pa5 is pulled low, the scc is programmed for internal clocks and the tclk1 and rclk1 pins are programmed to three-state to avoid contention with user clocks. the risc proces- sor then programs the scon register of the scc based on pa12. the pa12 value sampled during reset (modclk0) is decoded in order to provide ~9600 bps with two input frequen- cies (4.192 mhz and 32.768 khz). if modclk0 = gnd, scon1 is programmed to 0x00d8.
system integration block (sib) motorola mc68lc302 reference manual 3-9 if modclk0 = vcc, scon1 is programmed to 0x00a8. the following baud rates are achieved as a function of vccsyn, modclk, and input clock: vccsyn-modclk 00 20 mhz 11467 bps (scon1=0x00d8) 10 4.192 mhz 9614 bps (scon1=0x00d8) 10 4.8 mhz 11009 bps (scon1=0x00d8) 11 32.768 khz 9662 bps (scon1=0x00a8) the following paragraphs explain the boot process for the 32.768 khz case in detail. if the clock provided to the mc68lc302 is 32.768 khz, the system frequency is multiplied by 401 to get 13.139968 mhz. the cd10-cd0 bits of the scon are programmed to 84 decimal giv- ing a uart frequency of 9662. in summary, 13.139968 mhz / (84 + 1) / 16 = 9662. if the starting frequency is exactly 32.000 khz, the uart frequency is 9435. note the autobaud function cannot be used in the boot download pro- cess. values in bit cd10:0 in scon are not relevant if pa5=1 the risc processor then programs the scm register to $013d to program the scc to uart mode with both the receiver and the transmitter enabled, software operation mode (cd and cts are don't cares), 8-bit data characters, and no parity. the risc processor then begins receiving data into the dual-port ram beginning with location $0 of the dual-port ram. every character that is received is ?choed?back out of the txd1 pin. the mc68lc302 uart must be sent 576 bytes of data from the external uart since the lc302 will not leave the boot mode until 576 bytes are received. if the boot program is less than 576 bytes, the user is suggested to write $00 into the remaining locations. after 576 bytes are received, the risc programs the scm register to $0, which clears the enr and ent bits to disable the uart (returns to its reset value). the risc processor next negates the halt signal to the core internally. the 68000 then reads the reset vector from the first location of the dual-port ram. in most cases, the code that is downloaded will enable the chip selects of the mc68lc302, initialize the mc68lc302 receive buffer descriptors of scc1 to continue receiving additional boot code into external system ram, and re-initialize the uart receiver. note the first 576 bytes also overlays the exception vector table, meaning that exception vectors will not work unless the user carefully maps the code around certain desired vectors and points those vectors into the 576 byte code space. in addition
system integration block (sib) 3-10 mc68lc302 reference manual motorola the stack pointer must point into the 576 bytes if any exceptions are to be taken within the boot code. all 68000 accesses to the dual port ram are visible externally on the address and data pins so program execution in the 576 byte code space can be monitored. after the boot process is completed by the user, it is suggested that the user issue the cp reset command to the cp command register (cr) before reinitializing the sccs. this will return the cp to its original state and eliminate any possible inconsistencies in the initializa- tion process. the risc cannot return to boot mode unless a system reset is executed with the pa7 pin asserted low. toggling of the pa7 pin when the device is not in system reset is allowed, and in this mode the pa7 pin can be used in its alternate functions. note the user may wish to disable the software watchdog timer (tim- er 3) in the initial boot code if a long delay (i.e. more than 10 sec- onds) can occur between the initial boot download and the rest of the download process. at the end of the boot from scc function, the following registers contain values that differ from their default reset values: icr = 0xc000 bar = 0x0000 scon1 = depends on mode. the scm1 register is reprogrammed to its reset value of 0x0 note during the boot from scc procedure no external master should acquire the bus. 3.4 dma control the imp includes seven on-chip dma channels, six serial dma (sdma) channels for the three serial communications controllers (sccs) and one idma. the sdma channels are discussed in the mc68302 user? manual . the idma is discussed in the following para- graphs. 3.4.1 mc68lc302 differences the dreq , dack , and done pins have been removed. the user must not program the idma for external request generation. the external bus exceptions, berr and retry, have been removed. only halt or an in- ternal berr generated by the hardware watchdog timer is supported.
system integration block (sib) motorola mc68lc302 reference manual 3-11 the rest of the functionality remains the same as for the mc68302. for details on the bus operation, please refer to the mc68302 user? manual. 3.4.2 idma registers (independent dma controller) the idma has six registers that define its specific operation. these registers include a 32- bit source address pointer register (sapr), a 32-bit destination address pointer register (dapr), an 8-bit function code register (fcr), a 16-bit byte count register (bcr), a 16-bit channel mode register (cmr), and an 8-bit channel status register (csr). 3.4.2.1 channel mode register (cmr) the cmr, a 16-bit register, is reset to $0000. bit 15?eserved for future use. eco?xternal control option (not used) 0 = if the request generation is programmed to be external in the reqg bits, the con- trol signals (dack and done ) are used in the source (read) portion of the transfer since the peripheral is the source. 1 = if the request generation is programmed to be external in the reqg bits, the con- trol signals (dack and done ) are used in the destination (write) portion of the transfer since the peripheral is the destination. intn?nterrupt normal 0 = when the channel has completed an operand transfer without error conditions, the channel does not generate an interrupt request to the imp interrupt controller. the done bit remains set in the csr. 1 = when the channel has completed an operand transfer without error conditions, the channel generates an interrupt request to the imp interrupt controller and sets done in the csr. inte?nterrupt error (only the internal berr signal will be used.) 0 = if a bus error occurs during an operand transfer either on the source read (bes) or the destination write (bed), the channel does not generate an interrupt to the imp interrupt controller. the appropriate bit remains set in the csr. 1 = if a bus error occurs during an operand transfer either on bes or bed, the channel generates an interrupt to the imp interrupt controller and sets the appropriate bit (bes or bed) in the csr. reqg?equest generation (external request is not supported) 00 = internal request at limited rate (limited burst bandwidth) set by burst transfer (bt) bits 01 = internal request at maximum rate (one burst) 10 = external request burst transfer mode (dreq level sensitive) 11 = external request cycle steal (dreq edge sensitive) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 eco intn inte reqg sapi dapi ssize dsize bt rst str
system integration block (sib) 3-12 mc68lc302 reference manual motorola note the settings 10 and 11 will not work since the dreq pin is not present. sapi?ource address pointer (sap) increment 0 = sap is not incremented after each transfer. 1 = sap is incremented by one or two after each transfer, according to the source size (ssize) bits and the starting address. dapi?estination address pointer (dap) increment 0 = dap is not incremented after each transfer. 1 = dap is incremented by one or two after each transfer, according to the destination size (dsize) bits and the starting address. ssize?ource size 00 = reserved 01 = byte 10 = word 11 = reserved dsize?estination size 00 = reserved 01 = byte 10 = word 11 = reserved bt?urst transfer 00 = idma gets up to 75% of the bus bandwidth. 01 = idma gets up to 50% of the bus bandwidth. 10 = idma gets up to 25% of the bus bandwidth. 11 = idma gets up to 12.5% of the bus bandwidth. rst?oftware reset 0 = normal operation 1 = the channel aborts any external pending or running bus cycles and terminates channel operation. setting rst clears all bits in the csr and cmr. str?tart operation 0 = stop channel; clearing this bit will cause the idma to stop transferring data at the end of the current operand transfer. the idma internal state is not altered. 1 = start channel; setting this bit will allow the idma to start (or continue if previously stopped) transferring data. note str is cleared automatically when the transfer is complete.
system integration block (sib) motorola mc68lc302 reference manual 3-13 3.4.2.2 source address pointer register (sapr) the sapr is a 32-bit register. note that a23-a20 must be initialized by the user. they are driven internally by the idma and can be used by the chip selects for address comparison. 3.4.2.3 destination address pointer register (dapr) the dapr is a 32-bit register. note that a23-a20 must be initialized by the user. they are driven internally by the idma and can be used by the chip selects for address comparison. 3.4.2.4 function code register (fcr) the fcr is an 8-bit register. the function codes must e initialized by the user. the function code value programmed into the fcr is driven on the internal fc2-0 signals during a bus cycle to further qualify the ad- dress bus value. these values may be used by the chip selects for address matching. note this register is undefined following power-on reset. the user should always initialize it and should not use the function code value ?11?in this register. 3.4.2.5 byte count register (bcr) this 16-bit register specifies the amount of data to be transferred by the idma; up to 64k bytes (bcr = 0) is permitted. 3.4.2.6 channel status register (csr) the csr is an 8-bit register used to report events recognized by the idma controller. on recognition of an event, the idma sets its corresponding bit in the csr (regardless of the inte and intn bits in the cmr). bits 7??hese bits are reserved for future use. 31 24 23 0 reserved source address pointer 31 24 23 0 reserved destination address pointer 7 6 4 3 2 0 1 dfc 1 sfc 7 4 3 2 1 0 reserved dns bes bed done
system integration block (sib) 3-14 mc68lc302 reference manual motorola dns?one not synchronized (not used) bes?us error source this bit indicates that the idma channel terminated with an error during the read cycle. bed?us error destination this bit indicates that the idma channel terminated with an error during the write cycle. done?ormal channel transfer done this bit indicates that the idma channel has terminated normally. 3.5 interrupt controller the imp interrupt controller accepts and prioritizes both internal and external interrupt re- quests and generates a vector number during the cpu interrupt acknowledge cycle. 3.5.1 interrupt controller key differences since the function code pins are not connected externally, the mc68lc302 (with the core enabled) should be programmed to dedicated mode and to internally generate the vectors for levels 1, 6, and 7. an external device will not be able to decode an iack cycle and pro- vide an vector back to the mc68lc302. in disable cpu mode, the irq1 , irq6 , and irq7 become the br , bgack , and bg signals. with the core disabled, the mc68lc302 will not be able to decode an external cpu? inter- rupt acknowledge cycle. the user must poll the interrupt pending register (ipr) during in- terrupt handling to determine which peripheral caused the interrupt. 3.5.2 interrupt controller programming model the user communicates with the interrupt controller using four registers. the global interrupt mode register (gimr) defines the interrupt controller's operational mode. the interrupt pending register (ipr) indicates which inrq interrupt sources require interrupt service. the interrupt mask register (imr) allows the user to prevent any of the inrq interrupt sources from generating an interrupt request. the interrupt in-service register (isr) provides a ca- pability for nesting inrq interrupt requests. 3.5.2.1 global interrupt mode register (gimr) the user normally writes the gimr soon after a total system reset. the gimr is initially $0000 and is reset only upon a total system reset. mod?ode (the mode should be set to dedicated) 0 = normal operational mode. interrupt request lines are configured as ipl2 ?pl0 . 1 = dedicated operational mode. interrupt request lines are configured as irq7 , irq6 , and irq1 . 15 14 13 12 11 10 9 8 7 5 4 0 mod iv7 iv6 iv1 et7 et6 et1 v7?5 reserved
system integration block (sib) motorola mc68lc302 reference manual 3-15 iv7?evel 7 interrupt vector (internal vector generation should be used) 0 = internal vector. 1 = external vector. iv6?evel 6 interrupt vector (internal vector generation should be used) 0 = internal vector. 1 = external vector. iv1?evel 1 interrupt vector (internal vector generation should be used) 0 = internal vector. 1 = external vector. et7?rq7 edge-/level-triggered 0 = level-triggered. an interrupt is made pending when irq7 is low. note the m68000 always treats level 7 as an edge-sensitive interrupt. 1 = edge-triggered. an interrupt is made pending when irq7 changes from one to zero (falling edge). et6?rq6 edge-/level-triggered 0 = level-triggered. an interrupt is made pending when irq6 is low. 1 = edge-triggered. an interrupt is made pending when irq6 changes from one to zero (falling edge). et1?rq1 edge-/level-triggered 0 = level-triggered. an interrupt is made pending when irq1 is low. 1 = edge-triggered. an interrupt is made pending when irq1 changes from one to zero (falling edge). v7?5?nterrupt vector bits 7? these three bits are concatenated with five bits provided by the interrupt controller, which indicate the specific interrupt source, to form an 8-bit interrupt vector number. if these bits are not written, the vector $0f is provided. note: these three bits should be greater than or equal to ?10?in order to put the interrupt vector in the area of the exception vector ta- ble for user vectors. bits 11 and 4??eserved for future use. 3.5.2.2 interrupt pending register (ipr) each bit in the 16-bit ipr corresponds to an inrq interrupt source. when an inrq interrupt is received, the interrupt controller sets the corresponding bit in the ipr.
system integration block (sib) 3-16 mc68lc302 reference manual motorola note the err bit is set if the user drives the ipl2 ?pl0 lines to inter- rupt level 4 and no inrq interrupt is pending. 3.5.2.3 interrupt mask register (imr) each bit in the 16-bit imr corresponds to an inrq interrupt source. the user masks an in- terrupt source by clearing the corresponding bit in the imr. 3.5.2.4 interrupt in-service register (isr) each bit in the 16-bit isr corresponds to an inrq interrupt source. in a vectored interrupt environment, the interrupt controller sets the isr bit when the vector number corresponding to the inrq interrupt source is passed to the core during an interrupt acknowledge cycle. the user's interrupt service routine should clear this bit during the servicing of the interrupt. 15 14 13 12 11 10 9 8 pb11 pb10 scc1 sdma idma scc2 timer1 7 6 5 4 3 2 1 0 pb9 timer2 scp timer3 smc1 smc2 pb8 err 15 14 13 12 11 10 9 8 pb11 pb10 scc1 sdma idma scc2 timer1 7 6 5 4 3 2 1 0 pb9 timer2 scp timer3 smc1 smc2 pb8
system integration block (sib) motorola mc68lc302 reference manual 3-17 3.6 parallel i/o ports the imp supports three general-purpose i/o ports, port a, port b, and port n, whose pins can be general-purpose i/o pins or dedicated peripheral interface pins. some port b pins are always maintained as four general-purpose i/o pins, each with interrupt capability. 3.6.1 parallel i/o port differences the following port pins were removed: pa11, pa13, pa14, pa15, pb0, pb1, pb2, and pb4. if these signals are programmed to be inputs, the corresponding values in the data registers will be indeterminate. if these pins are programmed to be output, then the output value will be read back in the data register. the scp pins are now multiplexed onto pa8, pa9, and pa10. the modclk pin is multiplexed with the pa12 port pin. after reset, this pin becomes a gen- eral purpose i/o pin. an 8-bit port, port n, has been added. port n is only available when the mc68lc302 is in 8-bit mode (internal busw=0). 3.6.2 port a each of the port a pins are independently configured as a general-purpose i/o pin if the cor- responding port a control register (pacnt) bit is cleared. port a pins are configured as ded- icated on-chip peripheral pins if the corresponding pacnt bit is set.when acting as a general-purpose i/o pin, the signal direction for that pin is determined by the corresponding control bit in the port a data direction register (paddr). the port i/o pin is configured as an input if the corresponding paddr bit is cleared; it is configured as an output if the corre- sponding paddr bit is set. the padat register is used to read and write values for the port a pins. all pacnt bits and paddr bits are cleared on total system reset, configuring all port a pins as general-purpose input pins. 15 14 13 12 11 10 9 8 pb11 pb10 scc1 sdma idma scc2 timer1 0 7 6 5 4 3 2 1 0 pb9 timer2 scp timer3 smc1 smc2 pb8 0
system integration block (sib) 3-18 mc68lc302 reference manual motorola # allows a single external clock source on the rclk pin to clock both the scc receiver and transmitter. 3.6.3 port b port b has 12 pins; however only eight are connected externally. 3.6.3.1 pb7?b3 each port b pin may be configured as a general-purpose i/o pin or as a dedicated peripheral interface pin. pb7?b3 is controlled by the port b control register (pbcnt), the port b data direction register (pbddr), and the port b data register (pbdat), and pb7 is configured as an open-drain output (wdog ) upon total system reset. table 3-3 shows the dedicated function of each pin. the third column shows the input to the peripheral when the pin is used as a general-purpose i/o pin. 3.6.3.2 pb11?b8 pb11?b8 are four general-purpose i/o pins continuously available as general-purpose i/ o pins and, therefore, are not referenced in the pbcnt. pb8 operates like pb11?b9 ex- cept that it can also be used as the dram refresh controller request pin, as selected in the system control register (scr). table 3-2. port a pin functions pacnt bit = 1 pin function pacnt bit = 0 pin function input to scc2/scc3/idma rxd2 pa0 gnd txd2 pa1 rclk2 pa2 gnd tclk2 pa3 rclk2 # cts2 pa4 gnd rts2 pa5 cd2 pa6 gnd sds2/brg2 pa7 sprxd pa8 gnd sptxd pa9 spclk pa10 gnd na pa12 table 3-3. port b pin functions pbcnt bit = 1 pin function pbcnt bit = 0 pin function input to interrupt control and timers tin1 pb3 gnd tin2 pb5 gnd tout2 pb6 wdog pb7
system integration block (sib) motorola mc68lc302 reference manual 3-19 note if the pit is enabled, then the pb8 pin will not generate an inter- rupt, since the pit uses the pb8 interrupt in the ipr, imr, and isr. the direction of each pin is determined by the corresponding bit in the pbddr. the port pin is configured as an input if the corresponding pbddr bit is cleared; it is configured as an output if the corresponding pbddr bit is set. pbddr11?bddr8 are cleared on total sys- tem reset, configuring all pb11?b8 pins as general-purpose input pins.when a pb11?b8 pin is configured as an input, a high-to-low change will cause an interrupt request signal to be sent to the imp interrupt controller. 3.6.4 port n when the lc302 is in 8-bit mode (internal busw=0), 8 more general purpose i/o pins are available. the signal direction for each pin is determined by the corresponding control bit in the port n data direction register (pnddr). the port i/o pin is configured as an input if the corresponding pnddr bit is cleared; it is configured as an output if the corresponding pnd- dr bit is set. the pndat register is used to read and write values for the port n pins. 3.6.5 port registers the i/o port consists of three memory-mapped read-write 16-bit registers for port a and three memory-mapped read-write 16-bit registers for port b. refer to figure 3-2. parallel i/ o port registers for the i/o port registers. the reserved bits are read as zeros. 0 = i/o 1 = peripheral 0 = input 1 = output 0 = i/o 1 = peripheral port a control register(pacnt ) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - ca - ca ca ca ca ca ca ca ca ca ca ca port a data direction register(paddr) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - da - da da da da da da da da da da da port a data register(padat) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - - - pa - pa pa pa pa pa pa pa pa pa pa pa port b control register(pbcnt) 15 8 7 6 5 4 3 2 1 0 reserved cb cb cb - cb - - -
system integration block (sib) 3-20 mc68lc302 reference manual motorola 0 = input 1 = output 0 = input 1 = output figure 3-2. parallel i/o port registers 3.7 timers the imp includes four timer units: two identical general-purpose timers, a software watch- dog timer, and a periodic interrupt timer (pit). each general-purpose timer consists of a timer mode register (tmr), a timer capture regis- ter (tcr), a timer counter (tcn), a timer reference register (trr), and a timer event register (ter). the tmr contains the prescaler value programmed by the user. the software watch- dog timer, which has a watchdog reference register (wrr) and a watchdog counter (wcn), uses a fixed prescaler value. 3.7.1 mc68lc302 general purpose timer difference the only difference between the mc68lc302 and the mc68302 general purpose timers is that timer 1 output signal is not connected to the externally. 3.7.2 general purpose timers programming mode 3.7.2.1 timer mode register (tmr1, tmr2) tmr1 and tmr2 are identical 16-bit registers. tmr1 and tmr2, which are memory- mapped read-write registers to the user, are cleared by reset. rst?eset timer 0 = reset timer (software reset), includes clearing the tmr, trr, and tcn. 1 = enable timer port b data direction register(pbddr) 15 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved db db db db db db db - db - - - p ort b data register(pbdat) 15 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved pb pb pb pb pb pb pb - pb - - - port n data direction register(pnddr) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 dn dn dn dn dn dn dn dn reserved port n data register (pndat) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 pn pn pn pn pn pn pn pn reserved 15 8 7 6 5 4 3 2 1 0 prescaler value (ps) ce om ori frr iclk rst
system integration block (sib) motorola mc68lc302 reference manual 3-21 iclk?nput clock source for the timer 00 = stop count 01 = master clock 10 = master clock divided by 16 11 = corresponding tin pin, tin1 or tin2 (falling edge) frr?ree run/restart 0 = free run?imer count continues to increment after the reference value is reached. 1 = restart?imer count is reset immediately after the reference value is reached. ori?utput reference interrupt enable 0 = disable interrupt for reference reached 1 = enable interrupt upon reaching the reference value om?utput mode (only available for timer 1) 0 = active-low pulse for one clko clock cycle (60 ns at 16.67 mhz) 1 = toggle output ce?apture edge and enable interrupt 00 = capture function is disabled 01 = capture on rising edge only and enable interrupt on capture event 10 = capture on falling edge only and enable interrupt on capture event 11 = capture on any edge and enable interrupt on capture event ps?rescaler value the prescaler is programmed to divide the clock input by values from 1 to 256. the value 00000000 divides the clock by 1; the value 11111111 divides the clock by 256. 3.7.2.2 timer reference registers (trr1, trr2) each trr is a 16-bit register containing the reference value for the timeout. trr1 and trr2 are memory-mapped read-write registers. 3.7.2.3 timer capture registers (tcr1, tcr2) each tcr is a 16-bit register used to latch the value of the counter during a capture opera- tion when an edge occurs on the respective tin1 or tin2 pin. tcr1 and tcr2 appear as memory-mapped read-only registers to the user. 3.7.2.4 timer counter (tcn1, tcn2) tcn1 and tcn2 are 16-bit up-counters. each is memory-mapped and can be read and writ- ten by the user. a read cycle to tcn1 and tcn2 yields the current value of the timer and does not affect the counting operation. 3.7.2.5 timer event registers (ter1, ter2) each ter is an 8-bit register used to report events recognized by any of the timers. on rec- ognition of an event, the timer will set the appropriate bit in the ter, regardless of the cor- responding interrupt enable bits (ori and ce) in the tmr. ter1 and ter2, which appear
system integration block (sib) 3-22 mc68lc302 reference manual motorola to the user as memory-mapped registers, may be read at any time. a bit is cleared by writing a one to that bit (writing a zero does not affect a bit's value). cap?apture event the counter value has been latched into the tcr. the ce bits in the tmr are used to enable the interrupt request caused by this event. ref?utput reference event the counter has reached the trr value. the ori bit in the tmr is used to enable the interrupt request caused by this event. bits 7??eserved for future use. 3.7.3 timer 3 - software watchdog timer a watchdog timer is used to protect against system failures by providing a means to escape from unexpected input conditions, external events, or programming errors. timer 3 may be used for this purpose. once started, the watchdog timer must be cleared by software on a regular basis so that it never reaches its timeout value. upon reaching the timeout value, the assumption may be made that a system failure has occurred, and steps can be taken to re- cover or reset the system. no changes have been made to the software watchdog timer. please refer to the mc68302 users?manual for more information. 3.7.3.1 software watchdog reference register (wrr) wrr is a 16-bit register containing the reference value for the timeout. the en bit of the register enables the timer. wrr appears as a memory-mapped read-write register to the user. 3.7.3.2 software watchdog counter (wcn) wcn, a 16-bit up-counter, appears as a memory-mapped register and may be read at any time. clearing en in wrr causes the counter to be reset and disables the count operation. a read cycle to wcn causes the current value of the timer to be read. a write cycle to wcn causes the counter and prescaler to be reset. a write cycle should be executed on a regular basis so that the watchdog timer is never allowed to reach the reference value during normal program operation. 3.7.4 periodic interrupt timer (pit) the mc68lc302 imp provides a timer to generate periodic interrupts for use with a real- time operating system or the application software. the periodic interrupt time period can vary from 122 m s to 128 s (assuming a 32.768-khz crystal is used to generate the general system clock). this function can be disabled. 7 2 1 0 reserved ref cap 15 1 0 reference value en
system integration block (sib) motorola mc68lc302 reference manual 3-23 3.7.4.1 overview the periodic interrupt timer consists of an 11-bit modulus counter that is loaded with the val- ue contained in the pitr. the modulus counter is clocked by the clkin signal derived from the imp extal pin. see figure 2-2. the clock source is divided by four before driving the modulus counter (pitclk). when the modulus counter value reaches zero, an interrupt request signal is generated to the imp in- terrupt controller. the value of bits 11? in the pitr is then loaded again into the modulus counter, and the counting process starts over. a new value can be written to the pitr only when the pit is disabled. the pit interrupt replaces the imp pb8 interrupt and is mapped to the pb8 interrupt priority level 4. the pit interrupt is maskable by setting bit1 (pb8) in the imr register. note when the pit is enabled, pb8 can still be used as parallel i/o pin or as dram refresh controller request pin, but pb8 will not be capable of generating interrupts. 3.7.4.2 periodic timer period calculation the period of the periodic timer can be calculated using the following equation: solving the equation using a crystal frequency of 32.768 khz with the prescaler disabled gives: this gives a range from 122 m s, with a pitr value of $0, to 250 ms, with a pitr value of $7ff (assuming 32.768 khz at the extal pin. periodic interrupt timer period pitr count value+1 extal () 1 or 512 () 4 () ------------------------------------------------------ - ------------------------------------------------------- = periodic interrupt timer period pitr count value+1 32768 1 2 2 --------------------- - ------------------------------------------------- = periodic interrupt timer period pitr count value 8192 ------------------------------------------ - =
system integration block (sib) 3-24 mc68lc302 reference manual motorola solving the equation with the prescaler enabled (ptp=1) gives the following values: this gives a range from 62.5 ms, with a pitr value of $0 to 128 s, with a pitr value of $7ff. for a fast calculation of periodic timer period using a 32.768-khz crystal, the following equa- tions can be used: with prescaler disabled: programmable interrupt timer period = pitr (122 m s) with prescaler enabled: programmable interrupt timer period = pitr (62.5 ms) 3.7.4.3 using the periodic timer as a real-time clock the periodic interrupt timer can be used as a real-time clock interrupt by setting it up to gen- erate an interrupt with a one-second period. when using a 32.768-khz crystal, the pitr should be loaded with a value of $0f with the prescaler enabled to generate interrupts at a one-second rate. the interrupt is generated, in this case, at a precise 1 second rate, even if the interrupt is not serviced immediately. a true real time clock is obtained if the current in- terrupt is serviced completely before the next one occurs. 3.7.4.4 periodic interrupt timer register (pitr) the pitr contains control for prescaling the periodic timer as well as the count value for the periodic timer. this register can be read or written only during normal operational mode. bits 14?3 are not implemented and always return a zero when read. a write does not affect these bits. pitr $0f0 read/write 15 14 13 12 11 10 9 8 pten 0 0 ptp pitr10 pitr9 pitr8 pitr7 reset 0 0 0 00000 7 6 5 4 3 2 1 0 pitr6 pitr5 pitr4 pitr3 pitr2 pitr1 pitr0 res reset 0 0 0 0 0 0 0 0 periodic interrupt timer period pitr count value 32768 512 2 2 --------------------------- - ------------------------------------------ - = periodic interrupt timer period pitr count value 16 ------------------------------------------ - =
system integration block (sib) motorola mc68lc302 reference manual 3-25 pten?eriodic timer enable this bit contains the enable control for the periodic timer. 0 = periodic timer is disabled 1 = periodic timer is enabled ptp?eriodic timer prescaler control this bit contains the prescaler control for the periodic timer. 0 = periodic timer clock is not prescaled 1 = periodic timer clock is prescaled by a value of 512 pitr10??eriodic interrupt timer register bits these bits of the pitr contain the remaining bits of the pitr count value for the periodic timer. these bits may be written only when the pit is disabled (pten=0) to modify the pit count value. note if the pit is enabled with the ptp bit is set, the first interrupt can be up to 512 clocks early, depending on the prescaler counter value when the pit is enabled. 3.8 external chip-select signals and wait-state logic the imp provides a set of four programmable chip-select signals. each chip-select signal has an identical internal structure. for each memory area, the user may also define an in- ternally generated cycle termination signal (dtack ). this feature eliminates board space that would be necessary for cycle termination logic. the chip-select logic is active for memory cycles generated by internal bus masters (m68000 core, idma, sdma, dram refresh) or external bus masters (a23-a20 are driven to zero internally and fc2-0 are driven to 5) . these signals are driven externally on the falling edge of as and are valid shortly after as goes low. note for more information on the operation of the chip selects, please refer to section 3 of the mc68302 users?manual . note internal masters (cpu, idma and sdma) drive a23:a20 and fc2-fc0 internally. the cs logic compares the signals to the values programmed in the registers. in disable cpu mode or for external bus masters, the a23-a20 signals are internally driven to zero, so the user must program
system integration block (sib) 3-26 mc68lc302 reference manual motorola the corresponding bits in the chip select registers to zero, or mask off those address bits. also fc2-0 are driven to 5, so we suggest that the function code comparison be turned off. 3.8.1 chip-select registers each of the four chip-select units has two registers that define its specific operation. these registers are a 16-bit base register (br) and a 16-bit option register (or) (e.g., br0 and or0). the br should normally be programmed after the or since the br contains the chip- select enable bit. 3.8.1.1 base register (br3?r0) these 16-bit registers consist of a base address field, a read-write bit, and a function code field. fc2?c0 ?unction code field this field is contained in bits 15?3 of each br. these bits are used to set the address space function code. because of the priority mechanism and the en bit, only the cs0 line is active after a system reset. bits 12??ase address these bits are used to set the starting address of a particular address space. rw?ead/write 0 = the chip-select line is asserted for read operations only. 1 = the chip-select line is asserted for write operations only. en?nable 0 = the chip-select line is disabled. 1 = the chip-select line is enabled. after system reset, only cs0 is enabled; cs3 ?s1 are disabled. in disable cpu mode, cs3 ?s0 are disabled at system reset. the chip select does not require disabling before changing its parameters. 3.8.1.2 option registers (or3?r0) these four 16-bit registers consist of a base address mask field, a read/write mask bit, a compare function code bit, and a dtack generation field. 15 13 12 2 1 0 fc2 ?c0 base address (a23?13) rw en 15 13 12 2 1 0 dtack base address mask (m23?13) mrw cfc
system integration block (sib) motorola mc68lc302 reference manual 3-27 bits 15?2?tack field these bits are used to determine whether dtack is generated internally with a program- mable number of wait states or externally by the peripheral. bits 12??ase address mask these bits are used to set the block size of a particular chip-select line. the address com- pare logic uses only the address bits that are not masked (i.e., mask bit set to one) to de- tect an address match. 0 = the address bit in the corresponding br is masked. 1 = the address bit in the corresponding br is not masked. mrw?ask read/write 0 = the rw bit in the br is masked. 1 = the rw bit in the br is not masked. note for correct operation of the cs logic, mrw bit cannot be set in slave mode or in systems where an external master can take ownership of the bus. cfc?ompare function code 0 = the fc bits in the br are ignored. 1 = the fc bits on the br are compared. note compare function code may be useful in systems where only internal masters (cpu or dma) take ownership of the bus be- cause those masters drive the fc2-0 signals internally. in slave mode or in systems where external masters take ownership of the bus, cfc should be programmed to 0. table 3-4. dtack field encoding bits description 15 14 13 0 0 0 no wait state 0 0 1 1 wait state 0 1 0 2 wait states 0 1 1 3 wait states 1 0 0 4 wait states 1 0 1 5 wait states 1 1 0 6 wait states 1 1 1 external dtack
system integration block (sib) 3-28 mc68lc302 reference manual motorola 3.8.2 disable cpu logic (m68000) the imp can be configured to operate solely as a peripheral to an external processor. in this mode, the on-chip m68000 cpu should be disabled by strapping discpu high during sys- tem reset (reset and halt asserted simultaneously). the internal accesses to the imp peripherals and memory may be asynchronous or synchronous. during synchronous reads, one wait state may be used if required (emws bit set). the following pins change their func- tionality in this mode: 1. the ipl0 pin becomes br and is an output from the idma and sdma to the external m68000 bus. 2. the ipl2 pin becomes bg and is an input to the idma and sdma from the external m68000 bus. when bg is sampled as low by the imp, it waits for as , halt , and bgack to be negated, and then asserts bgack and performs one or more bus cy- cles. 3. the ipl1 pin becomes bgack and is an output from the idma and sdma to indicate bus ownership. 4. the ipl2-0 lines are no longer encoded interrupt lines.the interrupt controller will out- put the mc68lc302? interrupt request on iout2 . cs0 , which is multiplexed with iout2 is not available in this mode. 5. the weh and wel signals become uds and lds respectively. 6. the oe becomes r/w . discpu should remain continuously high during disable cpu mode operation. although the cs0 pin is not available as an output from the device in disable cpu mode, it may be en- abled to provide dtack generation. in disable cpu mode, br0 is initially $c000. in disable cpu mode, accesses by an external master to the imp ram and registers may be asynchronous or synchronous to the imp clock. see the sam and emws bits in the scr for details. 3.8.3 bus arbitration logic both internal and external bus arbitration are discussed in the following paragraphs. 3.8.3.1 internal bus arbitration the imp bus arbiter supports three bus request sources in the following standard priority: 1. external bus master (br pin) (only in disable cpu mode) 2. sdma for the sccs (six channels) 3. idma (one channel) 3.8.3.2 external bus arbitration when the cpu is enabled, an external bus master may gain ownership of the m68000 bus by asserting the halt signal. this will cause the lc302 bus master (m68000 core, sdma, or idma) to stop at the completion of the current bus cycle after asserting the halt signal, the external bus master must wait until as is negated plus 2 additional system clocks before accessing the bus (to allow the lc302 to threestate all of the bus signals).after gaining own-
system integration block (sib) motorola mc68lc302 reference manual 3-29 ership, the external master can not access the internal imp registers or ram. chip selects and system control functions, such as the hardware watchdog, continue to operate. when an external master desires to gain ownership, the following bus arbitration protocol should be used: 1. assert halt . 2. wait two system clocks. 3. if as is negated go to step 5. 4. wait for as negation. then wait two additional system clocks. 5. execute access (now the bus is guaranteed to be threestated) 6. when done, threestate bus and negate halt . note the rmcst bit in the scr should be zero for this arbitration procedure to work correctly. also, the external master cannot access the internal address space of the mc68lc302. bus arbitration is not supported when the mc68lc302 is in one of the low power modes. the chip does not release the address and data lines. 3.9 dynamic ram refresh controller the communications processor (cp) main (risc) controller may be configured to handle the dynamic ram (dram) refresh task without any intervention from the m68000 core. use of this feature requires a timer or scc baud rate generator (either from the imp or external- ly), the i/o pin pb8, and two transmit buffer descriptors from scc2 (tx bd6 and tx bd7). no changes have been made to the dram controller. for more information, please refer to the mc68302 users?manual .
system integration block (sib) 3-30 mc68lc302 reference manual motorola
motorola mc68lc302 reference manual 4-1 section 4 communications processor (cp) the cp includes the following modules: main controller (risc processor) four serial direct memory access (sdma) channels a command set register serial channels physical interface including: ?otorola interchip digital link (idl) ?eneral circuit interface (gci), also known as iom-2 ?ulse code modulation (pcm) highway interface ?onmultiplexed serial interface (nmsi) implementing standard modem signals two independent full duplex serial communication controllers (sccs) supporting the following protocols: ?igh-level/synchronous data link control (hdlc/sdlc) ?niversal asynchronous receiver transmitter (uart) ?utobaud function to detect baud rate of the incoming asynchronous bit stream ?inary synchronous communication (bisync) ?ransparent modes serial communication port (scp) for synchronous communication two serial management controllers (smcs) to support the idl and gci management channels 4.1 mc68lc302 key differences from the mc68302 scc3 was removed. the scp is now multiplexed with the pa8, pa9, and pa10 pins. the ddcmp and v.110 protocols were removed. the autobaud function was added for detecting the baud rate of the incoming asyn- chronous bit stream. this section only presents a description of features and registers that have changed or been added. features that have not changed such as uart, hdlc, biysync transparent, the smcs, and the scp will not be discussed. for more information on any function not dis- cussed in this section, please refer to the mc68302 user? manual . this section assumes that the user is familiar with the different protocols. for more informa- tion on a specific protocol implementation, please refer to the mc68302 user? manua l
communications processor (cp) 4-2 mc68lc302 reference manual motorola 4.2 serial channels physical interface the serial channels physical interface joins the physical layer serial lines to the two sccs and the two smcs. (the separate three-wire scp interface is described in serial commu- nication port (scp) on page 25.) the imp supports five different external physical interfaces from the sccs: 1. nmsi?onmultiplexed serial interface 2. pcm?ulse code modulation highway 3. idl?nterchip digital link 4. gci?eneral circuit interface 4.2.1 serial interface registers there are two serial interface registers: simode and simask. the simode register is a 16-bit register used to define the serial interface operation modes. the simask register is a 16-bit register used to determine which bits are active in the b1 and b2 channels of isdn. 4.2.1.1 serial interface mode register (simode) . if the idl or gci mode is used, this register allows the user to support any or all of the isdn channels independently. any extra scc channel can then be used for other purposes in nmsi mode. the simode register is a memory-mapped read-write register cleared by reset. the changes to this reg- ister are marked in bold . setz?et l1txd to zero (valid only for the gci interface) 0 = normal operation 1 = l1txd output set to a logic zero (used in gci activation sync/scit?ync mode/scit select support (valid only in pcm mode) 0 = one pulse wide prior to the 8-bit data 1 = n pulses wide and envelopes the n-bit data the scit (special circuit interface t) interface mode is valid only in gci mode. 0 = scit support disabled 1 = scit d-channel collision enabled. bit 4 of channel 2 c/i used by the imp for receiv- ing indication on the availability of the s interface d channel. 15 14 13 12 11 10 9 8 setz sync/scit sdiag1 sdiag0 sdc2 sdc1 b2rb b2ra 76543210 b1rb b1ra drb dra msc3 msc2 ms1 ms0
communications processor (cp) motorola mc68lc302 reference manual 4-3 sdiag1?diag0?erial interface diagnostic mode (nmsi1 pins only) 00 = normal operation 01 = automatic echo 10 = internal loopback 11 = loopback control sdc2?erial data strobe control 2 0 = sds2 signal is asserted during the b2 channel 1 = sds1 signal is asserted during the b2 channel sdc1?erial data strobe control 1 0 = sds1 signal is asserted during the b1 channel 1 = sds2 signal is asserted during the b1 channel b2rb, b2ra?2 channel route in idl/gci mode or ch-3 route in pcm mode 00 = channel not supported 01 = route channel to scc1 10 = route channel to scc2 (if msc2 is cleared) 11 = route channel to scc3 (not supported in the mcmc68lc302) b1rb, b1ra?1 channel route in idl/gci mode or ch-2 route in pcm mode 00 = channel not supported 01 = route channel to scc1 10 = route channel to scc2 (if msc2 is cleared) 11 = route channel to scc3 (not supported in the mcmc68lc302) drb, dra?-channel route in idl/gci mode or ch-1 route in pcm mode 00 = channel not supported 01 = route channel to scc1 10 = route channel to scc2 (if msc2 is cleared) 11 = route channel to scc3 (not supported in the mc68lc302) msc3?cc3 connection ( not supported in the mc68lc302) msc2?cc2 connection 0 = scc2 is connected to the multiplexed serial interface (pcm, idl, or gci) chosen in ms1?s0. nmsi2 pins are all available for other purposes. 1 = scc2 is not connected to a multiplexed serial interface but is either connected di- rectly to the nmsi2 pins or not used. the choice of general-purpose i/o port pins versus scc2 functions is made in the port a control register. ms1?s0?ode supported 00 = nmsi mode 01 = pcm mode 10 = idl mode 11 = gci interface
communications processor (cp) 4-4 mc68lc302 reference manual motorola 4.2.1.2 serial interface mask register (simask) . the simask register, a memory-mapped read-write register, is set to all ones by reset. simask is used in idl and gci to determine which bits are active in the b1 and b2 channels. any combination of bits may be chosen. a bit set to zero is not used by the imp. a bit set to one signifies that the corresponding b channel bit is used for transmission and reception on the b channel. note that the serial data strobes, sd1 and sd2, are asserted for the entire 8-bit time slot inde- pendent of the setting of the bits in the simask register. note bit 0 of this register is the first bit transmitted or received on the idl/gci b1 channel. 4.3 serial communication controllers (sccs) the imp contains two independent sccs, each of which can implement different protocols. this configuration provides the user with options for controlling up to two independent full- duplex lines implementing bridges or gateway functions or multiplexing both sccs onto the same physical layer interface to implement a two channels on a time-division multiplexed (tdm) bus. each protocol-type implementation uses identical buffer structures to simplify programming. 4.3.1 scc configuration register (scon) each scc controller has a configuration register that controls its operation and selects its clock source and baud rate. this register has not been changed from the mc68302. 4.3.1.1 divide by 2 input blocks (new feature). the scc baud rate generators have 2 divide by 2 blocks added to them. with the divide by 2 blocks enabled, the vco out- put from the pll and the tin1 input clock can be divided by 2 before they are used by the brg to generate the serial clocks. the divide by two blocks can be enabled by setting the bcd bit in the iomcr register if the brg clock source is derived from the imp system clock, or by setting the brgdiv bit in the disc register if the brg clock source is derived from the tin pin. 4.3.2 disable scc1 serial clocks out (disc) the disable scc1 serial clocks out (disc) is an 16-bit read/write register. the upper 8 bits control: (1) enabling the divide by 2 prescaler for the baud rate generator from the tin1 pin, and (2) options for three stating thetclk1, and rclk1 pins. 15 8 7 0 b2 1514131211109876543210 woms extc tcs rcs cd10 cd9 cd8 cd7 cd6 cd5 cd4 cd3 cd2 cd1 cd0 div4
communications processor (cp) motorola mc68lc302 reference manual 4-5 disc base+$8ee 4.3.2.1 rclk1 and tclk1 pin options. tsrclk1 0 = rclk1 is driven on its pin when scc1 rclk is the baud rate generator output. 1 = rclk1 is three-state. tstclk1 0 = tclk1 is driven on its pin when scc1 rclk is the baud rate generator output. 1 = tclk1 is three-state. brgdiv enables and disables the divide by two block between the tin1 pin and the brg1 pres- caler input. 0 = the divide by two block is disabled. 1 = the divide by two block is enabled. 4.3.3 scc mode register (scm) each scc has a mode register. the functions of bits 5? are common to each protocol. the function of the specific mode bits varies according to the protocol selected by the mode1 mode0 bits. they are described in the relevant sections for each protocol type. each scm is a 16-bit, memory-mapped, read-write register. the scms are cleared by reset. only the mode bits have changed functionality. for more information on the other bits, please refer to the mc68302 users?manual . diag1?iag0?iagnostic mode 00 = normal operation (cts , cd lines under automatic control) 01 = loopback mode 10 = automatic echo 11 = software operation enr?enable receiver when enr is set, the receiver is enabled. when it is cleared, the receiver is disabled, and any data in the receive fifo is lost. if enr is cleared during data reception, the receiver aborts the current character. enr may be set or cleared regardless of whether serial 15 14 13 12 11 10 9 8 tstclk1 tsrclk1 brgdiv reset: 0 0000000 76543210 reset: 0 0000000 15 6543210 specific mode bits diag1 diag0 enr ent mode1 mode0
communications processor (cp) 4-6 mc68lc302 reference manual motorola clocks are present. to restart reception, the enter hunt mode command should be issued before enr is set again. ent?nable transmitter when ent is set, the transmitter is enabled; when ent is cleared, the transmitter is dis- abled. if ent is cleared, the transmitter will abort any data transmission, clear the transmit data fifo and shift register, and force the txd line high (idle). data already in the trans- mit shift register will not be transmitted. ent may be set or cleared regardless of whether serial clocks are present. mode1?ode0?hannel mode 00 = hdlc 01 = asynchronous (uart) 10 = reserved 11 = bisync, promiscuous transparent, and autobaud 4.3.4 scc data synchronization register (dsr) each dsr is a 16-bit, memory-mapped, read-write register. dsr specifies the pattern used in the frame synchronization procedure of the scc in the synchronous protocols. in the uart protocol it is used to configure fractional stop bit transmission. after reset, the dsr defaults to $7e7e (two flags); thus, no additional programming is necessary for the hdlc protocol. for bisync the contents of the dsr should be written before the channel is enabled. 4.3.5 buffer descriptors table data associated with each scc channel is stored in buffers. each buffer is referenced by a buffer descriptor (bd). bds are located in each channel's bd table (located in dual-port ram). there are two such tables for each scc channel: one is used for data received from the serial line; the other is used to transmit data.the format of the bds is the same for each scc mode of operation (hdlc, uart, bisync, and transparent) and for both transmit or receive. only the first field (containing status and control bits) differs for each protocol. the bd format is shown in figure 4-1. figure 4-1. scc buffer descriptor format note even though the address bus is only 20 bits, the full 32-bit point- er must be bits 24-32 must be zero, and bits 20-23 are used in 15 8 7 0 syn2 syn1 15 0 offset + 0 status and control offset + 2 data length offset + 4 high-order data buffer pointer (only lower 8 bits use, upper 8 bits must be 0) offset + 6 low-order data buffer pointer
communications processor (cp) motorola mc68lc302 reference manual 4-7 the chip select address comparison, so they should be pro- grammed to a value which will assert the desired chip select. 4.3.6 scc parameter ram memory map each scc maintains a section in the dual-port ram called the parameter ram. each scc parameter ram area begins at an offset $80 from each scc base area ($400 or $500) and continues through offset $bf. part of each scc parameter ram (offset $80?9a), which is identical for each protocol chosen, is shown in table 4-1. offsets $9c?bf comprise the protocol-specific portion of the scc parameter ram. the scc parameters have not changed functionality from the mc68302. # should be initialized by the user (m68000 core). ## modi?d by the cp following a cp or system reset. 4.3.7 interrupt mechanism the interrupt mechanism for each scc is the same as the mc68302. 4.3.8 uart controller the functionality of the uart controller has not changed. the new autobaud feature is dis- cussed in 4.3.9 autobaud controller (new). for any additional information on parameters, registers, and functionality, please refer to the mc68302 users?manual . 4.3.8.1 uart memory map. when configured to operate in uart mode, the imp over- lays the structure (see table 4-2) onto the protocol-specific area of that scc's parameter ram. refer to system configuration registers on page 5 for the placement of the three scc parameter ram areas and to table 4-1 for the other parameter ram values table 4-1. scc parameter ram memory map address name width description scc base + 80 # scc base + 81 # scc base + 82 # scc base + 84 ## scc base + 86 ## scc base + 87 ## scc base + 88 scc base + 8c scc base + 8e scc base + 90 ## scc base + 92 ## scc base + 93 ## scc base + 94 scc base + 98 scc base + 9a rfcr tfcr mrblr rbd# tbd# byte byte word word byte byte 2 words word word word byte byte 2 words word word rx function code tx function code maximum rx buffer length rx internal state reserved rx internal buffer number rx internal data pointer rx internal byte count rx temp tx internal state reserved tx internal buffer number tx internal data pointer tx internal byte count tx temp scc base + 9c scc base + bf first word of protocol-specific area last word of protocol-specific area
communications processor (cp) 4-8 mc68lc302 reference manual motorola # initialized by the user (m68000 core). 4.3.8.2 uart mode register. each scc mode register is a 16-bit, memory- mapped, read-write register that controls the scc operation. the read-write uart mode register is cleared by reset. 4.3.8.3 uart receive buffer descriptor (rx bd). the cp reports information about each buffer of received data by its bds. the rx bd is shown in figure 4-2. figure 4-2. uart receive buffer descriptor 4.3.8.4 uart transmit buffer descriptor (tx bd). data is presented to the cp for transmission on an scc channel by arranging it in buffers referenced by the channel's tx bd table. the tx bd shown in figure 4-3. figure 4-3. uart transmit buffer descriptor table 4-2. uart specific parameter ram address name width description scc base + 9c # scc base + 9e scc base + a0 # max_idl idlc brkcr word word word maximum idle characters (receive) temporary receive idle counter break count register (transmit) scc base + a2 # scc base + a4 # scc base + a6 # scc base + a8 # parec frmec nosec brkec word word word word receive parity error counter receive framing error counter receive noise counter receive break condition counter scc base + aa # scc base + ac # uaddr1 uaddr2 word word uart address character 1 uart address character 2 scc base + ae scc base + b0 # scc base + b2 # scc base + b4 # scc base + b6 # scc base + b8 # scc base + ba # scc base + bc # scc base + be # rccr character1 character2 character3 character4 character5 character6 character7 character8 word word word word word word word word word receive control character register control character 1 control character 2 control character 3 control character 4 control character 5 control character 6 control character 7 control character 8 15 14 13 12 11 10 9 8 7 6 5 0 tpm1 tpm0 rpm pen um1 um0 frz cl rtsm sl common scc mode bits 1514131211109876543210 offset + 0 e x w i c a m id br fr pr ov cd offset + 2 data length offset + 4 offset +6 rx buffer pointer (24-bits used, upper 8 bits must be 0) 1514131211109876543210 offset + 0 r x w i cr a p ct offset + 2 data length offset + 4 offset +6 tx buffer pointer (24-bits used, upper 8 bits must be 0)
communications processor (cp) motorola mc68lc302 reference manual 4-9 4.3.8.5 uart event register. the scc event register (scce) is called the uart event register when the scc is operating as a uart. 4.3.8.6 uart mask register. the scc mask register (sccm) is referred to as the uart mask register when the scc is operating as a uart. if a bit in the uart mask reg- ister is a one, the corresponding interrupt in the event register will be enabled. if the bit is zero, the corresponding interrupt in the event register will be masked. this register is cleared upon reset. 4.3.9 autobaud controller (new) the autobaud function determines the baud rate and format of an asynchronous data stream starting with a known character. this controller may be used to implement the stan- dard at command set or other characters. in order to use the autobaud mode, the serial communication controller (scc) is initially pro- grammed to bisync mode. the scc receiver then synchronizes on the falling edge of the start bit. once a start bit is detected, each bit received is processed by the autobaud controller. the autobaud controller measures the length of the start bit to determine the receive baud rate and compares the length to values in a user supplied lookup table. after the baud rate is determined, the autobaud controller assembles the character and compares it against two user-defined characters. if a match is detected, the autobaud controller inter- rupts the host and returns the determined nominal start value from the lookup table. the autobaud controller continues to assemble the characters and interrupt the host until the host stops the reception process. the incoming message should contain a mixture of even and odd characters so that the user has enough information to decide on the proper char- acter format (length and parity). the host then uses the returned nominal start value from the lookup table, modifies the scc configuration register (scon) to generate the correct baud rate, and reprograms the scc to uart mode. many rates are supported including: 150, 300, 600, 1200, 2400, 4800, 9600, 14.4k, 19.2k, 38.4k, 57.6k, 64k, 96k, 115.2k and 230k. to estimate the performance of the autobaud mode, the performance table in appendix a can be used. the maximum full-duplex rate for a bisync channel is one-tenth of the system clock rate. so a 25 mhz imp can support 230k autobaud rate with another low-speed channel (<50 kbps) and a 20 mhz imp can support 115.2k autobaud rate with 2 low-speed channels. the performance can vary depending on system loading, configuration, and echoing mode. it is important that the highest priority scc be used for the autobaud function, since it is run- ning at a very high rate. any scc that is guaranteed to be idle during the search operation of the autobaud process will not impact the performance of autobaud in an application. idle is defined as not having any transmit or receive requests to/from the scc fifos. 4.3.9.1 autobaud channel reception process. the interface between the auto- baud controller and the host processor is implemented with shared data structures in the 76543210 cts cd idl brk ccr bsy tx rx
communications processor (cp) 4-10 mc68lc302 reference manual motorola scc parameter ram and in external memory and through the use of a special command to the scc. the autobaud controller uses receive buffer descriptor number 7 (rx bd7) for the autobaud command descriptor. this rx bd is initialized by the host to contain a pointer to a lookup table residing in the external ram (contains the maximum and nominal start bit length for each baud rate). the host also prepares two characters against which the autobaud control- ler will compare the received character (usually these characters are ??and ?? and the host initializes a pointer to a buffer in external memory where the assembled characters will be stored until the host stops the autobaud process. finally, the host initializes the scc data synchronization register (dsr) to $7fff in order to synchronize on the falling edge of the start bit. once the data structures are initialized, the host programs the scon register to provide a sampling clock that is 16x the maximum supported baud rate. the host then issues the enter_baud_hunt command and enables the scc in the bisync mode. the autobaud controller reception process begins when the start bit arrives. the auto- baud controller then begins to measure the start bit length. with each byte received from the scc that ?elongs?to the start bit, the autobaud controller increments the start length counter and compares it to the current lookup table entry. if the start length counter passed the maximum bit length defined by the current table entry, the autobaud controller switches to the next lookup table entry (the next slower baud rate). this process goes on until the autobaud controller recognizes the end of the start bit. then, the autobaud controller starts the character assembly process. the character assembly process uses the nominal bit length, taken from the current lookup table entry, to sample each incoming bit in it? center. each bit received is stored to form an 8-bit character. when the assembly process is completed (a stop bit is received), the char- acter is compared against two user-defined characters. if the received character does not match any of the two user defined characters, the auto- baud controller re-enters the enter_baud_hunt process. the host is not notified until a match is encountered. if a match is found, the character is written to the received control character register (rccr) with the corresponding status bit set in rx bd7. the channel will generate the control char- acter received (ccr) interrupt (bit 3 in the scce), if enabled. if the character matched, but a framing error was detected on the stop bit, the autobaud controller will also set the fram- ing error status bit in rx bd7. the autobaud controller then continues to assemble the incoming characters and to store them in the external data buffer. the host receives a ccr interrupt after each character is received.the host is responsible for determining the end of the incoming message (for example, a carriage return), stopping the autobaud process, and reprogramming the scc to uart mode. the autobaud controller returns the nominal start bit length value for the detected baud rate from the lookup table and a pointer to the last character received that was written to the external data buffer. the host must be able to handle each character inter-
communications processor (cp) motorola mc68lc302 reference manual 4-11 rupt in order to determine parity and character length (this information may be overwritten when the next character interrupt is presented to the host). the host uses the two received characters to determine 1) whether a properly formed ?t?or ?t?was received, and 2) the proper character format (character length, parity). once this is decided, three possible actions can result. first, the host may decide that the data received was not a proper ?t?or ?t? and issue the enter_baud_hunt command to cause the autobaud controller to resume the search process. second, the host may decide the ?t?or ?t?is proper and simply continue to receive characters in bisync mode. third, the m68000 core may decide that the ?t?or ?t?is proper, but a change in character length or parity is required. 4.3.9.2 autobaud channel transmit process. the autobaud microcode pack- age supports two methods for transmission. the first method is automatic echo which is sup- ported directly in the scc hardware, and the second method is a smart echo or software transmit which is supported with an additional clock and software. automatic echo is enabled by setting the diag bits in the scc mode register (scm) to ?0 and asserting the cd pin (externally on scc1 and on scc2 and scc3, either externally or by leaving the pin as a general purpose input). the ent bit of the scc should remain cleared. the transmitter is not used, so this echoing method does not impact performance. the smart echo or software transmit requires use of an additional clock and the transmitter, so the overall performance could be affected if other sccs are running. this method requires an additional clock for sampling the incoming bit stream since the baud rate gener- ator (brg) must be used to provide the correct frequency for transmission. the user needs to provide the sampling clock that will be used for the autobaud function on the rclk pin (for example, a 1.8432 mhz clock for 115.2k). the clock that will be used for the scc trans- mission can be provided to the brg from the system clock or on tin1.the tin1 and rclk1 pins can be tied together externally. after the first two characters have been received and character length and parity determined, the host programs the dsr to $ffff, enables the transmitter (by setting ent), and programs the transmit character descriptor (overlays con- trol character 8). the host is interrupted after each character is transmitted. for modem applications with the mc68lc302, scc2 will be used as the dte interface and autobauding to the dte baud rate will often be required. if use of the smart echo feature is desired, the receive clock can be provided by the baud rate generator 2 (brg2) internally by resetting the rcs bit in the scon2 register to zero. the separate transmit clock can be provided externally to the tclk2 pin through a hardwire connection. the tcs bit in the scon2 register should be set to one to enable the external clock source. after autobauding is complete, both the transmit and receive clock sources can be derived internally from brg2 and the external pin connected to tclk2 should be three stated to assure that it does not contend with the tclk2 pin. 4.3.9.3 autobaud parameter ram. when configured to operate in the autobaud mode, the imp overlays some entries of the uart-specific parameter ram as illustrated in table 4-3.
communications processor (cp) 4-12 mc68lc302 reference manual motorola * these values should be initialized by the user (m68000 core). note the new parameters that have been added to the table. they are max_bit, nom_start, abchr1, abchr2, rxptr (2 words), and txbd. these parameters are of special importance to the autobaud controller. they must be written prior to issuing the enter_baud_hunt command. when the channel is operating in the autobaud hunt mode, the max_bit parameter is used to hold the current maximum start bit length. the nom_start location contains the cur- rent nominal start from the lookup table. after the autobaud is successful and the first char- acter is matched, the user should use the nom_start value from the autobaud specific parameter ram to determine which baud rate from the lookup table was detected. also the tx internal data pointer (at offset scc base + 94) will point to the last character received into external data buffer. note when the channel is operating in the uart mode, the nom_start_/brkcr is used as the break count register and must be initialized before a stop_transmit command is is- sued. the characters abchr1 and abchr2 are the autobaud characters that should be searched for by the autobaud controller. typically these are ??and ??(i.e. $0061 and $0041) if using the hayes command set. these characters must be odd in order for the auto- baud controller to correctly determine the length of the start bit. characters are transmit- ted and received least significant bit first, so the autobaud controller detects the end of the start bit by the least significant bit of the character being a ?? table 4-3. autobaud specific parameter address name width description scc base + 9c * max_idl word maximum idle characters scc base + 9e max_bit word current maximum start bit length scc base + a0 nom_start word current nom. start bit (used to determine baud rate) scc base + a2 * parec word receive parity error counter scc base + a4 * frmec word receive framing error counter scc base + a6 * nosec word receive noise counter scc base + a8 * brkec word receive break error counter scc base + aa * abchr1 word user defined character1 scc base + ac * abchr2 word user defined character2 scc base + ae rccr word receive control character register scc base + b0 * character1 word control character1 scc base + b2 * character2 word control character2 scc base + b4 * character3 word control character3 scc base + b6 * character4 word control character4 scc base + b8 * character5 word control character5 scc base + ba * chr6/rxptr word contrchar6/msw of pointer to external rx buffer scc base + bc * chr7rxptr word contrchar7/lsw of pointer to external rx buffer scc base + be * chr8/txbd word control character8/transmit bd
communications processor (cp) motorola mc68lc302 reference manual 4-13 the rxptr is a 2 word location that contains a 32-bit pointer to a buffer in external memory used for assembling the received characters and must be initialized before the enter_baud_hunt command is issued. note since a length for this external buffer is not given, the user must provide enough space in memory for characters to be assem- bled and written until the autobaud process is to avoid overwrit- ing other data in memory. this location is not used as the character7 value in the control character table until the channel operates in normal uart mode. after reception begins in normal uart mode (i.e. the ??or ??is found), this entry is available again as a control character table entry. the txbd entry is used as the transmit character descriptor for smart echo or software transmit. this location is not used as the character8 value in the control character table until the channel operates in normal uart mode. after reception begins in normal uart mode (i.e. the ??or ??is found), this entry is available again as a control character table entry. 4.3.9.4 autobaud programming model. the following sections describe the details of initializing the autobaud microcode, preparing for the autobaud process, and the memory structures used. 4.3.9.4.1 preparing for the autobaud process. the host begins preparation for the auto- baud process with the following steps. steps 1 and 2 are required if the scc has been used after reset or after uart mode in order to re-enable the process. 1. disable the scc by clearing the enr and ent bits. (the host may wish to precede this action with the stop_transmit commands to abort transmission in an orderly way). 2. issue the enter_hunt_mode command to the scc (this ensures that an open buffer descriptor is closed). 3. set up all the autobaud parameters in the autobaud specific parameter ram shown in table 4-3, the autobaud command descriptor shown in table 4-4, and the lookup table shown in table 4-4. of these three areas, the autobaud controller only modifies the autobaud specific parameter ram and the first word of the autobaud command de- scriptor during its operation. 4. write the scon to configure the scc to use the baud rate generator clock of 16x the maximum supported baud rate. a typical value is $4000 assuming a 1.8432 mhz clock rate on tin1 and a maximum baud rate of 115.2k, but this can change depending on the maximum baud rate and the extal frequency. 5. write the dsr of the scc with the value $7fff in order to detect the start bit. 6. the host initiates the autobaud search process by issuing the enter_baud_hunt com- mand 7. write the scm of the scc with $1133 to configure it for bisync mode, with the revd
communications processor (cp) 4-14 mc68lc302 reference manual motorola and rbcs bits set, software operation mode, and the transmitter disabled. after a few characters have been received, the transmitter can be enabled, and the software echo function may be performed after issuing the restart transmit command. in general, the autobaud controller uses the same data structure as that of the uart con- troller. the first character (if matched) is stored in the receiver control character register and the external data buffer, and the status of that character is reported in the autobaud com- mand descriptor. after the first character, each incoming character is then stored in the buffer pointed to by rxptr, and the status is updated in the autobaud command autobaud descriptor. the tx internal data pointer (at offset scc base + 94) is updated to point to the last character stored in the external data buffer. 4.3.9.4.2 enter_baud_hunt command. this command instructs the autobaud controller to begin searching for the baud rate of a user predefined character. prior to issuing the com- mand the m68000 prepares the autobaud command descriptor to contain the lookup table size and pointer. the enter_baud_hunt uses the gci command with opcode = 10, and the channel number set for the corresponding scc. for example, with scc1, the value written to the command register would be $61. 4.3.9.4.3 autobaud command descriptor. the autobaud controller uses the receive buffer descriptor number 7 (rx bd7) as an autobaud command descriptor. the autobaud command descriptor is used by the m68000 core to transfer command parameters to the autobaud controller, and by the autobaud controller to report information concerning the received character. the structure of the autobaud command descriptor for the autobaud process is shown in table 4-4. the first word of the descriptor or the status word is updated after every character is received. fe ?framing error (bit 10) if this bit is set, a character with a framing error was received. a framing error is detected by the autobaud controller when no stop bit is detected in the received data. fe will be set for a 9-bit character (8 bits + parity) if the parity bit is ?? note the user must clear this bit when it is set. table 4-4. autobaud command descriptor offset 15 14 13 12 11 10 9 8 7654 3 2 1 0 0 fe m2 m1 eot ov cd 2 lookup table size 4 function code 8 lookup table pointer
communications processor (cp) motorola mc68lc302 reference manual 4-15 m2 ?match character2 (bit 9) when this bit is set, the character received matched the user defined character 2. the received character is written into the receive control character register (rccr). m1 ?match character1 (bit 8) when this bit is set, the character received matched the user defined character 1. the received character is written into the receive control character register (rccr). eot ?end of table (bit 3) when this bit is set, the autobaud controller measured start length exceeded the maxi- mum start length of the last entry in the lookup table (lowest baud rate). note the user must clear this bit when it is set. ov ?overrun (bit 1) if this bit is set, a receiver overrun occurred during autobaud reception. note the user must clear this bit when it is set. cd ?carrier detect lost (bit 0) if this bit is set, the carrier detect signal was negated during autobaud reception. note the user must clear this bit when it is set. lookup table size - lookup table size is the number of baud rate entries in the external lookup table. lookup table pointer - the lookup table pointer is the address in the external ram where the lookup table begins. note the lookup table cannot cross a 64k memory block boundary. 4.3.9.4.4 autobaud lookup table. the autobaud controller uses an external lookup table to determine the baud rate while in the process of receiving a character. the lookup table contains two entries for each supported baud rate. the first entry is the maximum start length for the particular baud rate, and the second entry is the nominal length for a 1/2 start bit. to determine the two values for each table entry, first calculate the autobaud sampling rate (eq 2). to do this eq 1 must be used until eq 2 is satisfied. the sampling rate is the lowest speed baud rate that can be generated by the scc baud rate generator that is over a thresh- old defined in eq 2. brg clk rate = system clock or tin1 / ((clock divider bits in scon) + 1) (eq 1)
communications processor (cp) 4-16 mc68lc302 reference manual motorola assuming that the div bit in scon is set to 0, (otherwise an additional ?ivide-by-4?must be included). sampling rate = brg clk rate, where brg clk rate >= (max desired uart baud rate) x 16 (eq 2) for instance, if a 115.2k baud rate is desired, with a 16.67 mhz system clock, the minimum sampling rate possible is 1.843 mhz = 115.2k x 16. this exact frequency can be input to rclk1 or tin1 as the sample clock. if the system clock is to be used, a 16.67 mhz system clock cannot produce an exact baud rate clock of 1.843 mhz. the lowest one that can be used is baud rate = 16.67 mhz / (7+1) = 2.083 mhz. thus, 2.083 mhz is the sampling rate, and the scon should be set to $000e to produce this. once the sampling rate is known, the other two equations follow easily. the maximum start bit length is calculated by the following equation: maximum start length = (sampling rate/recognized baud rate) x 1.05 (eq 3) thus, for the first entry in the table, the maximum start length is 1.8432 mhz/115200 x 1.05 = 17 for an external sample clock. the value 1.05 is a suggested margin that allows char- acters 5% larger than the nominal character rate to be accepted. in effect, the margin deter- mines the ?plit point?between what is considered to be a 56.7k character rate and what is a 38.4k character rate. the margin should not normally be less than 1.03 due to clocking differences between uarts. the nominal start bit length is calculated by: nominal start length = (sampling rate/recognized baud rate) / 2 (eq 4) for the 115.2k example in the first table entry, this would be 1.8432 mhz/115.2k/2 = 8. the structure of the lookup table is shown in table 4-5. the table starts with the maximum uart baud rate supported and ends with the minimum uart baud rate supported. note if less margin is used in the calculation of the maximum start length above, it is possible to distinguish between close uart rates such as 64k and 57.6k. however variations in rs232 driv- ers of up to 4%, plus nominal clocking rate variations of 3%, plus table 4-5. autobaud lookup table format offset from lookup table pointer description 0 maximum start length 2 nominal start length 4 maximum start length 6 nominal start length maximum start length nominal start length (lookup table size - 1) * 4 maximum start length [(lookup table size - 1) * 4] + 2 nominal start length
communications processor (cp) motorola mc68lc302 reference manual 4-17 the fact that the sampling rate may not perfectly divide into the desired uart rate, can make this distinction difficult to achieve in some scenarios. 4.3.9.5 lookup table example. table 4-6 is an example autobaud lookup table. the maximum start and nominal start val- ues are derived assuming a 1.8432 mhz sampling clock on tin1 or rclk and a shift factor of 5%. 4.3.9.6 determining character length and parity. table 4-7 shows the dif- ferent possible character lengths and parity that will be discussed. the following paragraphs will discuss for each case how to determine the parity. case 1?this case cannot be supported because the autobaud can not separate the first character from the second character. table 4-6. lookup table example desired baud rate maximum start nominal start 115200 17 8 57600 34 16 38400 50 24 28800 67 32 19200 101 48 14400 134 64 12000 161 77 9600 202 96 7200 269 128 4800 403 192 2400 806 384 1200 1613 768 600 3226 1536 300 6451 3072 110 17594 8378 table 4-7. character lengths and parity cases case # character length parity notes 1 7-bit no parity, 1 stop bit not supported 2 7-bit even parity odd parity parity=1 parity=0 parity is indicated by the most signif- icant bit of the byte 3 8-bit no parity same as 7-bit, parity=0 4 8-bit even parity odd parity parity=0 parity is indicated by which charac- ters generate a fe interrupt 5 8-bit parity=1 not supported
communications processor (cp) 4-18 mc68lc302 reference manual motorola case 2?as each character is assembled, it is stored into a complete byte. assuming that the characters are ascii characters with 7-bit codes, the 8th bit of the byte will con- tain the parity bit. if the parity is either even or odd, then after receiving an odd character and an even character, the 8th bit should be different for the odd and even characters. the parity can be determined by the setting of the parity bit for one of the two charac- ters. if the 8th bit is always a 1, this is the same as a 7-bit character, no parity and at least 2 stop bits or a 7-bit character with force 1 parity. if the 8th bit is always a zero, then either the character is a 7-bit character with force 0 parity, or the character is a 8- bit character with no parity. case 3?this case is the same as 7-bit character with force 0 parity. the 8th bit of the byte will always be zero. case 4?his case assumes a 8-bit character with the 8th bit of the character equal to a 0 (ascii character codes define the 8th bit as zero). if the parity is either even or odd, then after receiving an odd and an even character, a framing error (fe) interrupt should have been generated for one of them (the interrupt is generated when the parity bit is zero). the user can determine the parity by which character generated a fe interrupt (if the odd character did, then the parity is odd). if a framing error occurs on every char- acter, then the character is 8-bits with force 0 parity. if no framing error occurs, than this is the same as case 5. case 5?this case is not supported, because it can not be differentiated from 7-bit force 0 parity and 8-bit no parity. if the 9th bit is a 1, then it will be interpreted as a stop bit. 4.3.9.7 autobaud reception error handling procedure. the autobaud controller reports reception error conditions using the autobaud command descriptor. three types of errors are supported: carrier detect lost during reception when this error occurs and the channel is not programmed to control this line with software, the channel terminates reception, sets the carrier detect lost (cd) bit in the command descriptor, and generates the ccr interrupt, if enabled. ccr is bit 3 of the scce register. overrun error when this error occurs, the channel terminates reception, sets the overrun (ov) bit in the command descriptor, and generates the ccr interrupt, if enabled. end of table error when this error occurs, the channel terminates reception, sets the end of table (eot) bit in the command descriptor, and generates the ccr interrupt, if enabled. any of these errors will cause the channel to abort reception. in order to resume autobaud operation after an error condition, the m68000 should clear the status bits and issue the enter_baud_hunt command again. 4.3.9.8 autobaud transmission. the autobaud package supports two methods for echoing characters or transmitting characters. the two methods are automatic echo and smart echo.
communications processor (cp) motorola mc68lc302 reference manual 4-19 4.3.9.8.1 automatic echo. this method uses the scc hardware to automatically echo the characters back on the txd pin. the automatic echo is enabled by setting the diag bits in the scm to ?0? the transmitter should not be enabled. the hardware echo is done auto- matically. the cd pin needs to be asserted in order for the characters to be transmitted back. on scc1, the external cd pin must be tied low. on scc2 and scc3, either the exter- nal cd pin must be tied low or the cd pins should be left configured as general purpose input pins (the cd signal to the scc is then connected to ground internally). using the automatic echo, the receiver still autobauds correctly and performance is not affected. the scc echoes the received data with a few nanoseconds delay. 4.3.9.8.2 smart echo. this method requires addition hardware and software to implement. the user must provide two clock sources. one clock source is the sample clock which is input on rclk and cannot be divided down. the brg is used to divide the second clock down to provide the clock used for transmit. the second clock can be either the system clock or a clock connected to tin1. the tin1 and rclk pins can be connected to each other externally. after the first character is received, the user must take the following steps: 1. determine the baud rate from the returned nom_start value and program scon to (input frequency/baud rate)-1, where the input frequency is either the system clock or the clock on tin1. 2. program the dsr to $ffff. the dsr will need to be programmed back to $7fff be- fore the enter_baud_hunt command is issued again. 3. set the ent bit in the mode register. 4. program the transmit character bd as show in table 4-8. r (ready bit) 0 = character is not ready 1 = character is ready to transmit cl (character len) 0 = 7 bits + parity or 8 bits with no parity 1 = 8 bits + parity pe (parity enable) 0 = no parity 1 = parity 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r cl pe pm char table 4-8. transmit character bd
communications processor (cp) 4-20 mc68lc302 reference manual motorola pm (parity mode) 0 = even parity 1 = odd parity the autobaud controller issues a tx interrupt after each character is transmitted. 4.3.9.9 reprogramming to uart mode or another protocol. the following steps should be followed in order to switch the scc from autobaud to uart mode or to another protocol. disable the scc by clearing enr and ent. issue the enter_hunt_mode command. initialize the scc parameter ram (specifically, the rx and tx internal states and the words containing the rx and tx bd#s) to the state immediately after reset and initialize the protocol specific parameter area for the new protocol. re-enable the scc with the new mode. 4.3.10 hdlc controller the functionality of the hdlc controller has not changed. for any additional information on parameters, registers, and functionality, please refer to the mc68302 users?manual . 4.3.10.1 hdlc memory map . when configured to operate in hdlc mode, the imp over- lays the structure shown in table 4-8 onto the protocol-specific area of that scc parameter ram. refer to parameter ram on page 21 for the placement of the three scc parameter ram areas and to table 4-1 for the other parameter ram values. # should be initialized by the user (m68000 core). 4.3.10.2 hdlc mode register . each scc mode register is a 16-bit, memory-mapped, read-write register that controls the scc operation. the read-write hdlc mode register is cleared by reset. table 4-9. hdlc-specific parameter ram address name width description scc base + 9c scc base + 9e scc base + a0 # scc base + a2 # scc base + a4 scc base + a6 rcrc_l rcrc_h c_mask_l c_mask_h tcrc_l tcrc_h word word word word word word temp receive crc low temp receive crc high constant ($f0b8 16-bit crc, $debb 32-bit crc) constant ($xxxx 16-bit crc, $20e3 32-bit crc) temp transmit crc low temp transmit crc high scc base + a8 # scc base + aa # scc base + ac # scc base + ae # scc base + b0 # disfc crcec abtsc nmarc retrc word word word word word discard frame counter crc error counter abort sequence counter nonmatching address received counter frame retransmission counter scc base + b2 # scc base + b4 mflr max_cnt word word max frame length register max_length counter scc base + b6 # scc base + b8 # scc base + ba # scc base + bc # scc base + be # hmask haddr1 haddr2 haddr3 haddr4 word word word word word user-defined frame address mask user-defined frame address user-defined frame address user-defined frame address user-defined frame address
communications processor (cp) motorola mc68lc302 reference manual 4-21 4.3.10.3 hdlc receive buffer descriptor (rx bd) . the hdlc controller uses the rx bd to report information about the received data for each buffer. the rx bd is shown in figure 4-4. figure 4-4. hdlc receive buffer descriptor 4.3.10.4 hdlc transmit buffer descriptor (tx bd) . data is presented to the hdlc controller for transmission on an scc channel by arranging it in buffers referenced by the channel's tx bd table. the tx bd is shown in figure 4-5. figure 4-5. hdlc transmit buffer descriptor 4.3.10.5 hdlc event register . the scc event register (scce) is called the hdlc event register when the scc is operating as an hdlc controller. it is an 8-bit register used to report events recognized by the hdlc channel and to generate interrupts. upon recog- nition of an event, the hdlc controller sets its corresponding bit in the hdlc event register. interrupts generated by this register may be masked in the hdlc mask register. a bit is cleared by writing a one; writing a zero does not affect a bit's value. all unmasked bits must be cleared before the cp will clear the internal interrupt request. this register is cleared at reset. 4.3.10.6 hdlc mask register. the scc mask register (sccm) is referred to as the hdlc mask register when the scc is operating as an hdlc controller. it is an 8-bit read- write register that has the same bit formats as the hdlc event register. if a bit in the hdlc mask register is a one, the corresponding interrupt in the event register will be enabled. if the bit is zero, the corresponding interrupt in the event register will be masked. this register is cleared upon reset. 15 14 13 12 11 10 9 8 7 6 5 0 nof3 nof2 nof1 nof0 c32 fse rte flg enc common scc mode bits 1514131211109876543210 offset + 0 e x w i l f lgnoabcrovcd offset + 2 data length offset + 4 offset +6 rx buffer pointer (24-bits used, upper 8 bits must be 0) 151413121110987654321 0 offset + 0 r x w i l tc unct offset + 2 data length offset + 4 tx buffer pointer (24-bits used, upper 8 bits must be 0) offset + 6 76543210 cts cd idl txe rxf bsy txb rxb
communications processor (cp) 4-22 mc68lc302 reference manual motorola 4.3.11 bisync controller the functionality of the bisync controller has not changed. for any additional information on parameters, registers, and functionality, please refer to the mc68302 users?manual . 4.3.11.1 bisync memory map. when configured to operate in bisync mode, the imp overlays the structure listed in table 4-10 onto the protocol-specific area of that scc param- eter ram. refer to system configuration registers on page 5 for the placement of the three scc parameter ram areas and table 4-1 for the other parameter ram values. # initialized by the user (m68000 core). 4.3.11.2 bisync mode register. each scc mode register is a 16-bit, memory- mapped, read-write register that controls the scc operation. the term bisync mode reg- ister refers to the protocol-specific bits (15?) of the scc mode register when that scc is configured for bisync. the read-write bisync mode register is cleared by reset. 4.3.11.3 bisync receive buffer descriptor (rx bd). the cp reports information about the received data for each buffer using bd. the rx bd is shown in figure 4-6 figure 4-6. bisync receive buffer descriptor 4.3.11.4 bisync transmit buffer descriptor (tx bd). data is presented to the cp for transmission on an scc channel by arranging it in buffers referenced by the chan- nel's tx bd table. the tx bd is shown in figure 4-7. table 4-10. bisync specific parameter ram address name width description scc base + 9c scc base + 9e scc base + a0 # scc base + a2 scc base + a4 # scc base + a6 scc base + a8 rcrc crcc prcrc tcrc ptcrc res res word word word word word word word temp receive crc crc constant preset receiver crc 16/lrc temp transmit crc preset transmitter crc 16/lrc reserved reserved scc base + aa # scc base + ac # scc base + ae # parec bsync bdle word word word receive parity error counter bisync sync character bisync dle character scc base + b0 # scc base + b2 # scc base + b4 # scc base + b6 # scc base + b8 # scc base + ba # scc base + bc # scc base + be # character1 character2 character3 character4 character5 character6 character7 character8 word word word word word word word word control character 1 control character 2 control character 3 control character 4 control character 5 control character 6 control character 7 control character 8 15 14 13 12 11 10 9 8 7 6 5 0 pm exsyn ntsyn revd bcs rtr rbcs synf enc common scc mode bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 offset + 0 e x w i c b dl pr cr ov cd offset +2 data length offset +4 rx buffer pointer (24-bits used, upper 8 bits must be 0) offset + 6
communications processor (cp) motorola mc68lc302 reference manual 4-23 figure 4-7. bisync transmit buffer descriptor 4.3.11.5 bisync event register. the scc event register (scce) is referred to as the bisync event register when the scc is programmed as a bisync controller. it is an 8-bit register used to report events recognized by the bisync channel and to generate inter- rupts. on recognition of an event, the bisync controller sets the corresponding bit in the bisync event register. interrupts generated by this register may be masked in the bisync mask register. a bit is cleared by writing a one. more than one bit may be cleared at a time. all unmasked bits must be cleared before the cp will negate the internal interrupt request signal. this register is cleared at reset. 4.3.11.6 bisync mask register. the scc mask register (sccm) is referred to as the bisync mask register when the scc is operating as a bisync controller. it is an 8-bit read- write register that has the same bit format as the bisync event register. if a bit in the bisync mask register is a one, the corresponding interrupt in the event register will be enabled. if the bit is zero, the corresponding interrupt in the event register will be masked. this register is cleared upon reset. 4.3.12 transparent controller the functionality of the bisync controller has not changed. for any additional information on parameters, registers, and functionality, please refer to the mc68302 users?manual . 4.3.12.1 transparent memory map. when configured to operate in transparent mode, the imp overlays the structure illustrated in table 4-11 onto the protocol specific area of that scc parameter ram. refer to table 2-6 for the placement of the three scc param- eter ram areas and table 4-1 for the other parameter ram values. 1514131211109876543210 offset + 0 r x w i l tb b br td tr unct offset + 2 data length offset + 4 offset +6 tx buffer pointer (24-bits used, upper 8 bits must be 0) 76543210 cts cd txe rch bsy tx rx
communications processor (cp) 4-24 mc68lc302 reference manual motorola 4.3.12.2 transparent mode register. each scc mode register is a 16-bit, mem- ory-mapped, read-write register that controls the scc operation. the term transparent mode register refers to the protocol-specific bits (15?) of the scc mode register when that scc is configured for transparent mode. the transparent mode register is cleared by reset. all undefined bits should be written with zero. 4.3.12.3 transparent receive buffer descriptor (rxbd) . the cp reports information about the received data for each buffer using bd. the rxbd is shown in figure 4-8. figure 4-8. transparent receive buffer descriptor table 4-11. transparent-specific parameter ram address name width description scc base + 9c res word reserved scc base + 9e res word reserved scc base + a0 res word reserved scc base + a2 res word reserved scc base + a4 res word reserved scc base + a6 res word reserved scc base + a8 res word reserved scc base + aa res word reserved scc base + ac res word reserved scc base + ae res word reserved scc base + b0 res word reserved scc base + b2 res word reserved scc base + b4 res word reserved scc base + b6 res word reserved scc base + b8 res word reserved scc base + ba res word reserved scc base + bc res word reserved scc base + be res word reserved 15 14 13 12 11 10 9 8 7 6 5 0 exsyn ntsyn revd common scc mode bits 1514131211109876543210 offset + 0 e x w i ovcd offset + 2 data length offset + 4 offset +6 rx buffer pointer (24-bits used, upper 8 bits must be 0)
communications processor (cp) motorola mc68lc302 reference manual 4-25 4.3.12.4 transparent transmit buffer descriptor (tx bd) . data is pre- sented to the cp for transmission on an scc channel by arranging it in buffers referenced by the channel's tx bd table. the tx bd is shown in figure 4-9. figure 4-9. transparent transmit buffer descriptor 4.3.12.5 transparent event register . the scc event register (scce) is referred to as the transparent event register when the scc is programmed as a transparent control- ler. it is an 8-bit register used to report events recognized by the transparent channel and to generate interrupts. on recognition of an event, the transparent controller sets the corre- sponding bit in the transparent event register. a bit is cleared by writing a one (writing a zero does not affect a bit's value). this register is cleared at reset. 4.3.12.6 transparent mask register . the scc mask register (sccm) is referred to as the transparent mask register when the scc is operating as a transparent controller. it is an 8-bit read-write register that has the same bit format as the transparent event regis- ter. if a bit in the transparent mask register is a one, the corresponding interrupt in the event register will be enabled. if the bit is zero, the corresponding interrupt in the event register will be masked. this register is cleared at reset. 4.4 serial communication port (scp) the functionality of the scp has not changed. for any additional information on parameters, registers, and functionality, please refer to the mc68302 users?manual . 4.4.1 scp programming model the scp mode register consists of the upper eight bits of spmode. the scp mode regis- ter, an internal read-write register that controls both the scp operation mode and clock source, is cleared by reset. 1514131211109876543210 offset + 0 r x w i l unct offset + 2 data length offset + 4 offset +6 tx buffer pointer (24-bits used, upper 8 bits must be 0) 76543210 cts cd txe rch bsy tx rx 15 14 13 12 11 10 9 8 str ?loop ci pm3 pm2 pm1 pm0 en
communications processor (cp) 4-26 mc68lc302 reference manual motorola 4.4.2 scp transmit/receive buffer descriptor the transmit/receive bd contains the data to be transmitted (written by the m68000 core) and the received data (written by the scp). the done (d) bit indicates that the received data is valid and is cleared by the scp. 4.5 serial management controllers (smcs) the functionality of the smcs has not changed. for any additional information on parame- ters, registers, and functionality, please refer to the mc68302 users?manual . 4.5.1 smc programming model the operating mode of both smc ports is defined by smc mode, which consists of the lower eight bits of spmode. as previously mentioned, the upper eight bits program the scp. 4.5.2 smc memory structure and buffers descriptors the cp uses several memory structures and memory-mapped registers to communicate with the m68000 core. all the structures detailed in the following paragraphs reside in the dual-port ram of the imp. the smc buffer descriptors allow the user to define one data byte at a time for each transmit channel and receive one data byte at a time for each receive channel. 4.5.2.1 smc1 receive buffer descriptor. the cp reports information about the received byte using this (bd). 4.5.2.2 smc1 transmit buffer descriptor. the cp reports information about this transmit byte through the bd. 15 14 8 7 0 d reserved data 76543210 smd3 smd2 smd1 smd0 loop en2 en1 15 14 13 12 11 10 9 8 7 0 e l er ms ab eb data
communications processor (cp) motorola mc68lc302 reference manual 4-27 4.5.2.3 smc2 receive buffer descriptor. in the idl mode, this bd is identical to the smc1 receive bd. in the gci mode, smc2 is used to control the c/i channel. 4.5.2.4 smc2 transmit buffer descriptor. in the idl mode, this bd is identical to the smc1 transmit bd. in the gci mode, smc2 is used to control the c/i channel. 15 14 13 12 10 9 8 7 0 r l ar ab eb data 15 14 6 5 2 1 0 e reserved c/i 0 0 15 14 6 5 2 1 0 r reserved c/i 0 0
communications processor (cp) 4-28 mc68lc302 reference manual motorola
motorola mc68lc302 reference manual 5-1 section 5 signal description this section defines the mc68lc302 pinout. the input and output signals of the mc68lc302 are organized into functional groups and are described in the following sec- tions. the mc68lc302 is offered in a 100-lead thin quad flat package (tqfp) and a 132- pin (13 x 13) pin grid array (pga) for emulator applications. the mc68lc302 uses a m68000 like bus for communication between both on-chip and ex- ternal peripherals. this bus is a single, continuous bus existing both on-chip and off-chip the mc68lc302. any access made internal to the device is visible externally. any access made external is visible internally. thus, when the m68000 core accesses the dual-port ram, the bus signals are driven externally. likewise, in disable cpu mode, when an external device accesses an area of external system memory, the chip-select logic can be used to generate the chip-select signal and dtack . 5.1 functional groups the input and output signals of the mc68lc302 are organized into functional groups as shown in table 5-1 and figure 5-1. table 5-1. signal definitions (tqfp) functional group signals number clocks xtal, extal, xfc, clko,vccsyn 5 system control reset , halt , busw, discpu 4 address bus a19?1 19 data bus/pnio pn15-pn8/d15-d8 8 data bus d7-d0 8 bus control as ,oe (r/w ),weh (u ds /a0),wel (lds/ds ), dtack 5 interrupt control (bus arbitration) ipl2 ?pl0(br , bg , bgack) 3 nmsi1/isdn i/f rxd1, txd1, rclk1, tclk1, cd1 , cts1 , rts1 7 nmsi2/paio rxd2, txd2, rclk2, tclk2, cd2 , cts2 , rts2 , brg2 8 paio/scp sprxd, sptxd,spclk, modclk/pa12 4 timer/pbio tin1, tin2, tout2 , w dog 4 pbio pb11?b8 4 chip select cs3?s0 4 v dd 6 gnd 11
signal description 5-2 mc68lc302 reference manual motorola all pins except extal, clko, and the layer 1 interface pins in idl mode support ttl levels. extal, when used as an input clock, needs a cmos level. clko supplies a cmos level output. the idl interface is specified as a cmos electrical interface. all outputs (except clko and the gci pins) drive 100 pf. clko is designed to drive 50 pf. the gci output pins drive 100 pf. 5.2 power pins the lc302 (tqfp) has 17 power supply pins. careful attention has been paid to reducing lc302 noise, potential crosstalk, and rf radiation from the output drivers. inputs may be +5 v when v dd is 0 v without damaging the device. ? dd (6)?here are 6 power pins. gnd (11)?here are 11 ground pins.
signal description motorola mc68lc302 reference manual 5-3 figure 5-1. lc 302 functional signal groups data bus/port n d0-d7 d15-d8/pn15-8 a1-a19 lc302 bus control chip select reset halt busw discpu cs0 /iout2 cs3 -cs1 address bus rxd1/l1rxd rclk1/l1clk txd1/l1txd tclk1/l1sy0/sds1 cd1/ l1sy1 cts1 /l1gr rts1 /l1rq/gcidcl system control rxd2/pa0 rclk2/pa2 txd2/pa1 tclk2/pa3 cts2 /pa4 rts2 /pa5 boot /brg2/sds2/pa7 cd2 /pa6 sprxd/pa8 spclk/pa10 sptxd/pa9 modclkpa12 nmsi1/ isdn i/f nmsi2/ paio paio/ scp signals as wel /we (lds /ds ) weh /a0 (uds /a0) dtack oe (r/w ) xtal extal clko xfc clock pb8 pb9 pb10 pb11 interrupt control ipl0 /irq1 (br ) ipl2 /irq7 (bg ) ipl1 /irq6 (bgack ) tin1/pb3 tin2/pb5 tout2 /pb6 wdog /pb7 timer/pbio note: pins in parenthesis () are available in slave mode only. pins available in pga package fc2-0 frz iac avec
signal description 5-4 mc68lc302 reference manual motorola 5.3 clock pins the clock pins are shown in figure 5-2. figure 5-2. clock pins extal?xternal clock/crystal input this input provides two clock generation options (crystal and external clock). extal may be used (with xtal) to connect an external crystal to the on-chip oscillator and clock gen- erator. if an external clock is used, the clock source should be connected to extal, and xtal should be left unconnected. the oscillator uses an internal frequency equal to the external crystal frequency. the frequency of extal may range from 0 mhz to the maxi- mum operating frequency (25mhz at the time this manual was written). when an external clock is used, it must provide a cmos level at this input frequency. the frequency range of the original mc68lc302 is 0 mhz to the maximum operating fre- quency. in this manual, many references to the frequency ?6.67 mhz?are made when the maximum operating frequency of the mc68lc302 is discussed. when using faster versions of the mc68lc302, such as 20 mhz, all references to 16.67 mhz may be re- placed with 20. note, however, that resulting parameters such as baud rates and timer periods change accordingly. xtal?rystal output this output connects the on-chip oscillator output to an external crystal. if an external clock is used, xtal should be left unconnected. clko?lock out this output clock signal is derived from the on-chip clock oscillator. this clock signal is internally connected to the clock input of the m68000 core, the communication processor, and system integration block. all m68000 bus timings are referenced to the clko signal. clko supports both cmos and ttl output levels. the output drive capability of the clko signal is programmable to one-third, two-thirds, or full strength, or this output can be disabled. extal xtal clko xfc modclk/pa12 vccsyn gndsyn
signal description motorola mc68lc302 reference manual 5-5 xfc?mp external filter capacitor this pin is a connection for an external capacitor to filter the pll. modclk/pa12?lock mode select the state of this input signal along with vccsyn during reset selects whether the pll is enabled and the type of external clock that is used by the phase locked loop (pll) in the clock synthesizer to generate the system clocks. table 5-2 shows the default values of the pll. when the pll is disabled (vccsyn=0), this pin functions as pa12. when the pll is enabled (vccsyn1), this pin is sampled as modclk at reset.this pin must be valid as long as reset and halt are asserted, and have a hold time of 5ns after reset and halt are negated. after reset, modclk/pa12 is a general purpose i/o pin. vccsyn?nalog pll circuit power this pin is dedicated to the lc302 analog pll circuits and determines whether the pll is enabled or not. when this pin is connected to vcc, the pll is enabled, and when this pin is connected to ground, the pll is disabled. the voltage should be well regulated and the pin should be provided with an extremely low impedance path to the v cc power rail. v ccsyn should be bypassed to gnd by a 0.1 m f capacitor located as close as possible to the chip package. gndsyn?nalog pll circuits?ground this pin is dedicated to the imp analog pll circuits. the pin should be provided with an extremely low impedance path to ground. gndsyn should be bypassed to vccsyn by a 0.1 m f capacitor located as close as possible to the chip package. 5.4 system control pins the system control pins are shown in figure 5-3. table 5-2. default operation mode of the pll vccsyn modclk pll multi. factor (mf+1) extal freq. (examples) clkin to the pll lc302 system clock 0 x disabled x - =extal =extal 1 0 enabled 4 4.192mhz 4.192mhz 16.768 mhz 1 1 enabled 401 32.768khz 32.768khz 13.14 mhz
signal description 5-6 mc68lc302 reference manual motorola figure 5-3. system control pins reset this bidirectional, open-drain signal, acting as an input and asserted along with the halt pin, starts an initialization sequence called a total system reset that resets the entire mc68lc302. reset and halt should remain asserted for at least 100 ms at power-on reset, and at least 10 clocks otherwise. the on-chip system ram is not initialized during reset except for several locations initialized by the cp. note with a 32.768khz external crystal the minimum reset length is 2.3 seconds an internally generated reset, from the m68000 reset instruction, causes the reset line to become an output for 124 clocks. in this case, the m68000 core is not reset; how- ever, the communication processor is fully reset, and the system integration block is al- most fully rese. the user may also use the reset output signal in this case to reset all external devices. during a total system reset, the address, data, and bus control pins are all three-stated, except for cs3 ?s0 , weh , wel , and oe , which are high, and iac, which is low. the bg pin output is the same as that on the br input. the general-purpose i/o pins are config- ured as inputs, except for wdog , which is an open-drain output. the nmsi1 pins are all inputs, except for rts1 and txd1, which output a high value. clko is active. besides the total system reset and the reset instruction, some of the mc68lc302 pe- ripherals have reset bits in one of their registers that cause that particular peripheral to be reset to the same state as a total system reset or the reset instruction. reset bits may be found in the cp (in the cr), the idma (in the cmr), timer 1 (in the tmr1), and timer 2 (in the tmr2). halt ?alt when this bidirectional, open-drain signal is driven by an external device, it will cause the lc302 bus master (m68000 core, sdma, or idma) to stop at the completion of the current bus cycle. this signal is asserted with the reset signal to cause a total mc68lc302 sys- tem reset. this signal is also used to force the lc302 off the bus if another bus master * this pin is available in pga package only reset halt busw discpu frz
signal description motorola mc68lc302 reference manual 5-7 requires the bus, unless the lc302 core is disabled (then the br, bg, and bgack pins should be used). after asserting the halt signal, the external bus master must wait until as is negated plus 2 additional clocks before accessing the bus (to allow the lc302 to threestate all of the bus signals). busw?us width select this input defines the m68000 processor mode (mc68000 or mc68008) and the data bus width (16 bits or 8 bits, respectively). busw may only be changed upon a total system reset. in 16-bit mode, all accesses to internal and external memory by the mc68000 core, the idma, sdma, and external master may be 16 bits, according to the assertion of the uds and lds pins. in 8-bit mode, all m68000 core and idma accesses to internal and external memory are limited to 8 bits. also in 8-bit mode, sdma accesses to external memory are limited to 8 bits, but cp accesses to the cp side of the dual-port ram con- tinue to be 16 bits. in 8-bit mode, external accesses to internal memory are also limited to 8 bits at a time. low = 8-bit data bus, mc68008 core processor high = 16-bit data bus, mc68000 core processor discpu?isable cpu (m68000 core) the mc68lc302 can be configured to work solely with an external cpu. in this mode the on-chip m68000 core cpu should be disabled by asserting the discpu pin high during a total system reset (reset and halt asserted). discpu may only be changed upon a total system reset. the discpu pin, for instance, allows use of several lc302s to provide more than two scc channels without the need for bus isolation techniques. an external processor ser- vices the other lc302s as peripherals (with their respective cores disabled). frz the frz pin is used to freeze the activity of selected peripherals. this is useful for system debugging purposes. refer to 3.1.4 freeze control for more details. frz should be con- tinuously negated during total system reset. 5.5 address bus pins (a19?1) the address bus pins are shown in figure 5-4. figure 5-4. address bus pins a19-a1
signal description 5-8 mc68lc302 reference manual motorola a19?1 form a 20-bit address bus when combined with weh /uds . the address bus is a bidirectional, three-state bus capable of addressing 1m bytes of data (including the lc302 internal address space). it provides the address for bus operation during all cycles except cpu space cycles. in cpu space cycles, the cpu reads a peripheral device vector number. these lines are outputs when the lc302 (m68000 core, sdma or idma) is the bus master and are inputs otherwise (in discpu only). note: since internally the cs logic compares also a23-a20 the effec- tive address space for internal masters is 4 m bytes. 5.6 data bus pins (d15?0) the data bus pins are shown in figure 5-5. when the mc68lc302 is in 8-bit data bus mode, d15-d8 become general purpose i/o pins, pn15-pn8. figure 5-5. data bus pins this 16-bit, bidirectional, three-state bus is the general-purpose data path. it can transmit and accept data in either word or byte lengths. for all 16-bit lc302 accesses, byte 0, the high-order byte of a word, is available on d15?8, conforming to the standard m68000 for- mat. when working with an 8-bit bus (busw is low), the data is transferred through the low-order byte (d7?0). the high-order byte (d15?8) is not used for data transfer, and those pins can be used as 8 general purpose i/o ports (pnio). d0-d7 d15-d8/pn15-8
signal description motorola mc68lc302 reference manual 5-9 5.7 bus control pins the bus control pins are shown in figure 5-6. the signals shown in parentheses are only available in discpu mode. figure 5-6. bus control pins as ?ddress strobe this bidirectional signal indicates that there is a valid address on the address bus. this line is an output when the lc302 (m68000 core, sdma or idma) is the bus master and is an input otherwise. oe (r/w )?output enable (read/write) when the core is enabled, this output is active during a read cycle and indicates that an external device should place valid data on the bus. when the lc302 is in disable cpu mode, this bidirectional signal defines the data bus transfer as a read or write cycle. it is an output when the lc302 is the bus master and is an input otherwise. weh (uds /a0)?rite enable high (upper data strobe/address 0) when the core is enabled with a 16-bit data bus, this output pin functions as weh and is active during a write cycle to indicate that an external device should expect data on the d15-d8 of the data bus. when the core is enabled with a 8-bit data bus, this bidirectional pin functions as a0. when the lc302 is in disable cpu mode, this bidirectional line functions as uds and controls the flow of data on the data bus. when using a 16-bit data bus, this pin functions as an upper data strobe (uds ). when using an 8-bit data bus, this pin functions as a0. when used as a0 (i.e., the busw pin is low), then the pin takes on the timing of the other address pins, as opposed to the strobe timing. this line is an output when the lc302 is the bus master and is an input otherwise. as weh /a0 (uds/ a0) wel /we (lds /ds ) dtack oe (r/w ) iac* * this pin is available in pga package only
signal description 5-10 mc68lc302 reference manual motorola wel (lds/ds )?rite enable low (lower data strobe/data strobe) when the core is enabled, this output pin functions as wel and is active during a write cycle to indicate that an external device should expect data on the d7-d0 of the data bus. when the lc302 is in disable cpu mode, this bidirectional line functions as lds and con- trols the flow of data on the data bus. when using a 16-bit data bus, this pin functions as lower data strobe (lds ). when using an 8-bit data bus, this pin functions as ds . this line is an output when the lc302 (m68000 core, sdma or idma) is the bus master and is an input otherwise. dtack ?ata transfer acknowledge this bidirectional signal indicates that the data transfer has been completed. dtack can be generated internally in the chip-select logic either for an lc302 bus master or for an external bus master access to an external address within the chip-select ranges. it will also be generated internally during any access to the on-chip dual-port ram or internal registers. if dtack is generated internally, then it is an output. it is an input when the lc302 accesses an external device not within the range of the chip-select logic or when programmed to be generated externally. iac?nternal access the iac signal is only available in the pga package. this output indicates that the current bus cycle accesses an on-chip location. this includes the on-chip 4k byte block of internal ram and registers (both real and reserved locations), and the system configuration reg- isters ($0f0?0ff). the above-mentioned bus cycle may originate from the m68000 core, the idma, or an external bus master. note that, if the sdma accesses the internal dual-port ram, it does so without arbitration on the m68000 bus; therefore, the iac pin is not asserted in this case. the timing of iac is identical to that of the cs3 ?s0 pins. 5.8 bus arbitration pins the bus arbitration pins are shown in figure 5-7. these signals are only available in dis- able cpu mode. when the core is enabled, the bus arbitration signals are the ipl2-0 signals. figure 5-7. bus arbitration pins br ?us request this input signal indicates to the on-chip bus arbiter that an external device desires to be- come the bus master. bg bgack br
signal description motorola mc68lc302 reference manual 5-11 bg ?us grant this signal is an input to the idma and sdma when the internal m68000 core is disabled and indicates that the lc302 has the bus after the current bus cycle completes. bgack ?us grant acknowledge this bidirectional signal indicates that some device has become the bus master. this sig- nal is an input when an external device owns the bus. this signal is an output when the idma or sdma has become the master of the bus. if the sdma steals a cycle from the idma, the bgack pin will remain asserted continuously. note bgack should always be used in the external bus arbitration process. 5.9 interrupt control pins the interrupt control pins are shown in figure 5-8. the ipl2-0 signals are only available when the cpu is enabled. the fc2-0 and avec signals are only available in the pga package . figure 5-8. interrupt control pins these inputs have dual functionality: ipl0/irq1 ipl1/irq6 ipl2 /irq7 ?nterrupt priority level 2?/interrupt request 1,6,7 as ipl2 ?pl0 (normal mode), these input pins indicate the encoded priority level of the external device requesting an interrupt. level 7 is the highest (nonmaskable) priority; whereas, level 0 indicates that no interrupt is requested. the least significant bit is ipl0, and the most significant bit is ipl2 . these lines must remain stable until the m68000 core ipl0/irq1 ipl2/irq7 fc0* fc1* ipl1/irq6 fc2* avec* * those pins are available in pga package only
signal description 5-12 mc68lc302 reference manual motorola signals an interrupt acknowledge through a19?16 to ensure that the interrupt is properly recognized. as irq1 , irq6 , and irq7 (dedicated mode), these inputs indicate to the mc68lc302 that an external device is requesting an interrupt. level 7 is the highest level and cannot be masked. level 1 is the lowest level. each one of these inputs (except for level 7) can be programmed to be either level-sensitive or edge-sensitive. the m68000 always treats a level 7 interrupt as edge sensitive. fc2?c0?unction codes 2? these bidirectional signals indicate the state and the cycle type currently being executed. the information indicated by the function code outputs is valid whenever as is active. these lines are outputs when the imp (m68000 core, sdma, or idma) is the bus master and are inputs otherwise. the function codes output by the m68000 core are predefined; whereas, those output by the sdma and idma are programmable. the function code lines are inputs to the chip-select logic and imp internal register decoding in the bar. avec ?utovector input/interrupt output in normal operation, this signal functions as the input avec . avec , when asserted during an interrupt acknowledge cycle, indicates that the m68000 core should use automatic vectoring for an interrupt. this pin operates like vpa on the mc68000, but is used for au- tomatic vectoring only. avec instead of dtack should be asserted during autovectoring and should be high otherwise. 5.10 mc68lc302 bus interface signal summary table 5-3 and table 5-4 summarize all bus signals discussed in the previous paragraphs. they show the direction of each pin for the following bus masters: m68000 core, idma, sdma (includes dram refresh), and external bus masters. when the core is enabled, only the lc302 core has access to the internal memory. when the core is disabled, the idma, sdma, and external bus masters can access either internal dual-port ram and registers or an external device or memory. when an external bus master accesses the internal dual-port ram or registers, the access may be synchronous or asynchronous. external masters are only directly supported in the disable cpu mode. when the core is enabled and an external bus master needs the bus, then the halt pin must be asserted to the lc302 to halt the part.
signal description motorola mc68lc302 reference manual 5-13 1 external masters are only directly supported in disable cpu mode. 2 signal names in parentheses are only available in disable cpu mode. * weh ,wel ,oe are threestate when external master acquires the bus with halt **i f dt ack is generated automatically (internally) by the chip-select logic, then it is an output. otherwise, it is an input. 1 signal names in parentheses are only available in disable cpu mode. ** if dtack is generated automatically (internally) by the chip-select logic, then it is an output. otherwise, it is an input.#applies to disable cpu mode only. the internal signal ibclr is used otherwise. ## applies to disable cpu mode only, otherwise n/a. table 5-3. bus signal summary?ore and external master signal name 2 pin type m68000 core master access to external master access to 1 internal memory space external memory space internal memory space external memory space a19?1,as , u ds , l ds , rw i/o o o i i weh ,wel ,oe i/o o o o* o* d15?0 read i/o o i o i d15?0 write i/o o o i i dtack i/o o ** o ** (br ) i/o open drain na na n/a n/a (bg ) i na na n/a n/a (bgack ) i/o na na i i halt i/o open drain i/o i/o i i reset i/o open drain i/o i/o i i ipl2?pl0 iiinana avec iiiii iout2 ooooo table 5-4. bus signal summary?dma and sdma signal name 1 pin type idma master access to sdma master access to internal memory space external memory space internal memory space external memory space a19?1,as , u ds , l ds , rw i/o o o n/a o weh ,wel ,oe i/o o o n/a o d15?0 read i/o o i n/a i d15?0 write i/o o o n/a o dtack i/o o ** n/a ** (br ) i/o o ## o ## n/a o ## (bg ) i/o i ## i ## n/a i ## (bgack ) i/o o## o## n/a o## halt i/o open drain i i n/a i reset i/o open drain i i n/a i
signal description 5-14 mc68lc302 reference manual motorola 5.11 physical layer serial interface pins the physical layer serial interface has 18 pins, and all of them have multiple functions. the pins can be used in a variety of configurations in isdn or non-isdn environments. table 5- 4 shows the functionality of each group of pins and their internal connection to the two sccs and one scp controllers. the physical layer serial interface can be configured for non-mul- tiplexed operation (nmsi) or multiplexed operation that includes idl, gci, and pcm high- way modes. idl and gci are isdn interfaces. when working in one of the multiplexed modes, the nmsi1/isdn physical interface can be connected to both scc controllers. note: each one of the parallel i/o pins can be con?ured individually. 5.12 typical serial interface pin configurations table 5-5 shows typical configurations of the physical layer interface pins for an isdn envi- ronment. table 5-7 shows potential configurations of the physical layer interface pins for a non-isdn environment. the timer pins can be used in all applications either as dedicated functions or as pio pins. notes: 1. isdn environment with scp port for status/control exchange and with existing terminal (for rate adaption). 2. d-ch is used for signaling. 3. b-ch is used for voice (external codec required) or for data transfer. note: generic environment with two scc ports (any protocol) and the scp port. 5.13 nmsi1 or isdn interface pins the nmsi1 or isdn interface pins are shown in figure 5-9. table 5-5. serial interface pin functions first function connected to second function connected to nmsi1 (7) scc1 controller isdn interface scc1/scc2 nmsi2 (8) scc2 controller pio?ort a parallel i/o paio/scp (3) scp controller pio?ort a parallel i/o table 5-6. example isdn configuration pins connected to used as nmsi1 or isdn i/f scc1 and scc2 scc1 used as isdn d-ch scc2 used as isdn b-ch paio or scp pa12?a8 scp pio or status/control exchange table 5-7. typical generic configurations pins connected to used as nmsi1 or isdn i/f scc1 terminal with modem nmsi2 scc2 terminal with modem paio/scp scp status/control exchange
signal description motorola mc68lc302 reference manual 5-15 figure 5-9. nmsi1 or isdn interface pins these seven pins can be used either as nmsi1 in nonmultiplexed serial interface (nmsi) mode or as an isdn physical layer interface in idl, gci, and pcm highway modes. the in- put buffers have schmitt triggers. table 5-8 shows the functionality of each pin in nmsi, gci, idl, and pcm highway modes. notes: 1. in idl and gci mode, sds2 is output on the pa7 pin. 2. cd1 may be used as an external sync in nmsi mode. 3. r ts is the r ts1 , r ts2 , or r ts3 pin according to which sccs are connected to the pcm highway. rxd1/l1rxd?eceive data/layer-1 receive data this input is used as the nmsi1 receive data in nmsi mode and as the receive data input in idl, gci, and pcm modes. txd1/l1txd?ransmit data/layer-1 transmit data this output is used as nmsi1 transmit data in nmsi mode and as the transmit data output in idl, gci, and pcm modes. txd1 may be configured as an open-drain output in nmsi mode. l1txd in idl and pcm mode is a three-state output. in gci mode, it is an open- drain output. table 5-8. mode pin functions signal name nmsi1 gci idl pcm rxd1/l1rxd i rxd1 i l1rxd i l1rxd i l1rxd txd1/l1txd o txd1 o l1txd o l1txd o l1txd rclk1/l1clk i/o rclk1 i l1clk i l1clk i l1clk tclk1/l1sy0 i/o tclk1 o sds1 o sds1 i l1sy0 cd1 /l1sy1 i cd1 i l1sync i l1sync i l1sy1 cts1 /l1gr i cts1 i l1gr i l1gr rts1 /l1rq o rts1 o gcidcl o l1rq o rts rxd1 / l1rxd txd1 / l1txd rclk1 / l1clk tclk1 / l1sy0 / sds1 cd1 / l1sy1 rts1 / l1rq / gcidcl cts1 / l1gr
signal description 5-16 mc68lc302 reference manual motorola rclk1/l1clk?eceive clock/layer-1 clock this pin is used as an nmsi1 bidirectional receive clock in nmsi mode or as an input clock in idl, gci, and pcm modes. in nmsi mode, this signal is an input when scc1 is working with an external clock and is an output when scc1 is working with its baud rate generator. tclk1/l1sy0/sds1?ransmit clock/pcm sync/serial data strobe 1 this pin is used as an nmsi1 bidirectional transmit clock in nmsi mode, as a sync signal in pcm mode, or as the sds1 output in idl/gci modes. in nmsi mode, this signal is an input when scc1 is working with an external clock and is an output when scc1 is working with its baud rate generator. note when using scc1 in the nmsi mode with the internal baud rate generator operating, the tclk1 and rclk1 pins will always out- put the baud rate generator clock unless disabled in the ckcr register. thus, if a dynamic selection between an internal and external clock source is required in an application, the clock pins should be disabled first in the ckcr register before switching the tclk1 and rclk1 lines. on scc2, contention may be avoided by disabling the clock line outputs in the pacnt regis- ter. in pcm mode, l1sy1?1sy0 are encoded signals used to create channels that can be in- dependently routed to the sccs. note: ch-1, 2, and 3 are connected to the sccs as determined in the simode register. in idl/gci modes, the sds2?ds1 outputs may be used to route the b1 and/or b2 chan- nels to devices that do not support the idl or gci buses. this is configured in the serial in- terface mode (simode) and serial interface mask (simask) registers. cd1 /l1sy1?arrier detect/layer-1 sync this input is used as the nmsi1 carrier detect (cd ) pin in nmsi mode, as a pcm sync signal in pcm mode, and as an l1sync signal in idl/gci modes. if the cd1 pin has changed for more than one receive clock cycle, the lc302 asserts the appropriate bit in the scc1 event register. if the scc1 channel is programmed not to sup- port cd1 automatically (in the scc1 mode register), then this pin may be used as an ex- ternal interrupt source. the current value of cd1 may be read in the sccs1 register. see table 5-9. pcm mode signals l1sy1 l1sy0 data (l1rxd, l1txd) is routed to scc 0 0 l1txd is three-stated, l1rxd is ignored 0 1 ch-1 1 0 ch-2 1 1 ch-3
signal description motorola mc68lc302 reference manual 5-17 mc68302 user? manual for details. cd1 may also be used as an external sync in nmsi mode. cts1 /l1gr?lear to send/layer-1 grant this input is the nmsi1 cts signal in the nmsi mode or the grant signal in the idl/gci mode. if this pin is not used as a grant signal in gci mode, it should be connected to v dd . if the cts1 pin has changed for more than one transmit clock cycle, the lc302 asserts the appropriate bit in the scc1 event register and optionally aborts the transmission of that frame. if scc1 is programmed not to support cts1 (in the scc1 mode register), then this pin may be used as an external interrupt source. the current value of the cts1 pin may be read in the sccs1 register. see the mc68302 user? manual for details. rts1 /l1rq/gcidcl?equest to send/layer-1 request/gci clock out this output is the nmsi1 rts signal in nmsi mode or pcm highway mode, the idl re- quest signal in idl mode, or the gci data clock output in gci mode. in pcm highway mode, rts1 is asserted high. rts1 is asserted when scc1 (in nmsi mode) has data or pad (flags or syncs) to transmit. in gci mode this pin is used to output the gci data clock. 5.14 nmsi2 port or port a pins the nmsi2 port or port a pins are shown in figure 5-10. figure 5-10. nmsi2 port or port a pins these eight pins can be used either as the nmsi2 port or as a general-purpose parallel i/o port. each one of these pins can be configured individually to be general-purpose i/o pins or a dedicated function in nmsi2. when they are used as nmsi2 pins, they function exactly as the nmsi1 pins in nmsi mode. the pa7 signal in dedicated mode becomes serial data strobe 2 (sds2) in idl and gci modes. in idl/gci modes, the sds2?ds1 outputs may be used to route the b1 and/or b2 channels to devices that do not support the idl or gci buses. this is configured in the si- rxd2/pa0 rclk2/pa2 tclk2/pa3 cts2 /pa4 txd2/pa1 rts2 /pa5 cd2 /pa6 brg2/sdg2/pa7
signal description 5-18 mc68lc302 reference manual motorola mode and simask registers. if scc2 is in nmsi mode, this pin operates as brg2, the out- put of the scc2 baud rate generator, unless sds2 is enabled to be asserted during the b1 or b2 channels of isdn (bits sdc2?dc1 of simode). sds2/brg2 may be temporarily disabled by configuring it as a general-purpose output pin. the input buffers have schmitt triggers. tclk2 acts as the scc2 baud rate generator output if scc2 is in one of the mul- tiplexed modes. rxd2/pa0 txd2/pa1 rclk2/pa2 tclk2/pa3 cts2 /pa4 rts2 /pa5 cd2 /pa6 boot /sds2/pa7/brg2 note: in nmsi mode, the baud rate generator outputs can also appear on the rclk and tclk pins as programmed in the scon register. note pa7 and pa5 pins are sampled at initialization to determine the boot mode. to enable boot from scc2 mode, pa7 has to be pulled low during reset (with 5ns hold time after negation of reset and halt ). if boot mode is enabled, pa5 determines the clock source to scc2. this pin has to be valid for 100 clocks after the negation of reset and halt . the user can pull it high or low with an external resistor. if boot mode is not en- abled pa5 is not sampled at initialization. 5.15 paio / scp pins the nmsi3 port or port a pins or scp pins are shown in figure 5-11. table 5-10. baud rate generator outputs source nmsi gci idl pcm scc2 brg2 tclk2 tclk2 tclk2
signal description 5-19 mc68lc302 reference manual motorola figure 5-11. paio / scp pins these four pins can be used either as the scp port or parallel i/o pins. if the scp is enabled (en bit in spmode register is set), then the three lines must be connected to the scp port by setting the appropriate bits in the port a control register. otherwise, they are connected to the general purpose i/o. three of the port a i/o pins can be configured individually to be general-purpose i/o pins or a scp pin. sprxd/pa8?cp receive serial data/port a pin 8 this signal functions as the scp receive data input or may be used as a general purpose i/o pin. sptxd/pa9?cp transmit serial data/port a pin 9 this output is the scp transmit data output or may be used as a general purpose i/o pin. spclk/cd3 ?cp clock/nmsi3 cd pin this bidirectional signal is used as the scp clock output or may be used as a general pur- pose i/o pin. modclk/pa12 after total system reset this pin functions as bit 12 of port a. 5.16 timer pins the timer pins are shown in figure 5-12. figure 5-12. timer pins sprxd / pa8 sptxd / pa9 spclk / pa10 pa12 tin1 / pb3 tin2 / pb5 tout2 / pb6 wdog / pb7
signal description 5-20 mc68lc302 reference manual motorola each of these four pins can be used either as a dedicated timer function or as a general- purpose port b i/o port pin. note that the timers do not require the use of external pins. the input buffers have schmitt triggers. tin1/pb3?imer 1 input this input is used as a timer clock source for timer 1 or as a trigger for the timer 1 capture register. tin1 may also be used as the external clock source for any scc baud rate gen- erators. tin2/pb5?imer 2 input this input can be used as a timer clock source for timer 2 or as a trigger for the timer 2 capture register. tout2/pb6?imer 2 output this output is used as an active-low pulse timeout or as an event overflow output (toggle) from timer 2. wdog/pb7?atchdog output this active-low, open-drain output indicates expiration of the watchdog timer. wdog is asserted for a period of 16 clock (clko) cycles and may be externally connected to the reset and halt pins to reset the mc68lc302. the wdog pin function is enabled after a total system reset. it may be reassigned as the pb7 i/o pin in the pbcnt register. 5.17 parallel i/o pins with interrupt capability the four parallel i/o pins with interrupt are shown in figure 5-13. figure 5-13. port b parallel i/o pins with interrupt pb11?b8?ort b parallel i/o pins these four pins may be configured as a general-purpose parallel i/o ports with interrupt ca- pability. each of the pins can be configured either as an input or an output. when configured as an input, each pin can generate a separate, maskable interrupt on a high-to-low transi- tion. pb8 may also be used to request a refresh cycle from the dram refresh controller rath- er than as an i/o pin. the input buffers have schmitt triggers. pb8 pb9 pb10 pb11
signal description motorola mc68lc302 reference manual 5-21 5.18 chip-select pins the chip-select pins are shown in figure 5-14. figure 5-14. chip-select pins cs0/iout2?hip-select 0/interrupt output 2 in normal operation, this pin functions as cs0. cs0 is one of the four active-low output pins that function as chip selects for external devices or memory. it does not activate on accesses to the internal ram or registers (including the bar, scr, or ckcr registers). when the m68000 core is disabled, this pin operates as iout2. iout2 provides the in- terrupt request output signal from the lc302 interrupt controller to an external cpu when the m68000 core is disabled. this signal is asserted if an internal interrupt of level 4, 6, 7 is generated. cs3?s1?hip selects 3? these three active-low output pins function as chip selects for external devices or mem- ory. cs3?s0 do not activate on accesses to the internal ram or registers (including the bar scr, or ckcr registers). 5.19 when to use pullup resistors pins that are input-only or output-only do not require external pullups. the bidirectional bus control signals require pullups since they are three-stated by the mc68lc302 when they are not being driven. open-drain signals always require pullups. unused inputs should not be left floating. if they are input-only, they may be tied directly to v cc or ground, or a pullup or pulldown resistor may be used. unused outputs may be left unconnected. unused i/o pins may be configured as outputs after reset and left unconnect- ed. if the mc68lc302 is to be held in reset for extended periods of time in an application (other than what occurs in normal power-on reset or board test sequences) due to a special appli- cation requirement (such as v dd dropping below required specifications, etc.), then three- stated signals and inputs should be pulled up or down. this decreases stress on the device transistors and saves power. see the reset pin description for the condition of all pins during reset. cs0/iout2 cs3?s1
signal description 5-22 mc68lc302 reference manual motorola
motorola mc68lc302 reference manual 6-1 section 6 electrical characteristics the ac specifications presented consist of output delays , input setup and hold times , and signal skew times. all signals are specified relative to an appropriate edge of the clock (clko pin) and possibly to one or more other signals. the timing for the lc302 signals is the same as the corresponding signals of the 68302. very important note regarding signals a few signals have been added to and removed from the 68lc302 or their functionality has changed. several signals are only available when 68302 is in cpu disable mode.the iac, fc2-fc0, avec and frz signals are only available on the pga package. the a23-a20, rmc , berr , bclr , iack1 , iack6 , iack7 , dreq , dack , done , brg1, tout1 , nc1, nc3, tclk3, rts3 , cts3 , cd3 signals have been removed uds , lds , r/w , br , bg , bgack are available only in slave mode. the following diagrams and tables show the timing for all avail- able signals. for complete information on which signals are available in which modes (cpu disable), please refer to section 5 of this addendum.
electrical characteristics 6-2 mc68lc302 reference manual motorola 6.1 maximum ratings 6.2 thermal characteristics rating symbol value unit this device contains circuitry to protect the inputs against damage due to high static voltages or elec- tric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated volt- ages to his high-impedance circuit. reliability of operation is en- hanced if unused inputs are tied to an appropriate logic voltage level (e.g., either gnd or v dd ) supply voltage v dd - 0.3 to + 7.0 v input voltage v in - 0.3 to + 7.0 v operating temperature range mc68302 mc68302c t a 0 to 70 - 40 to 85 c storage temperature range t stg - 55 to + 150 c characteristic symbol value unit thermal resistance for pga q ja 25 c/w q jc 2 c/w thermal resistance for tqfp q ja tbd c/w q jc tbd c/w t j = t a + (p d a ) p d = (v dd i dd ) + p i/o where: p i/o is the power dissipation on pins. for t a = 70 c and p i/o + 0 w, 16.67 mhz, 5.5 v, and cqfp package, the worst case value of t j is: t j = 70 c + (5.5 v 30 ma 40 c/w) = 98.65c
electrical characteristics motorola mc68lc302 reference manual 6-3 6.3 power considerations the average chip-junction temperature , t j , in c can be obtained from: t j = t a + (p d ? q ja )(1) where: t a = ambient temperature , c q ja = package thermal resistance , junction to ambient , c/w p d =p int + p i/o p int =i dd x v dd , watts?hip internal power p i/o = power dissipation on input and output pins?ser determined for most applications p i/o < 0.3 p int and can be neglected. if p i/o is neglected , an approximate relationship between p d and t j is p d =k ? (t j + 273 c)(2) solving equations (1) and (2) for k gives: k=p d (t a + 273 c) + q ja ?p d 2 (3) where k is a constant pertaining to the particular part. k can be determined from equation (3) by measuring p d (at equilibrium) for a known t a . using this value of k , the values of p d and t j can be obtained by solving equations (1) and (2) iteratively for any value of t a .
electrical characteristics 6-4 mc68lc302 reference manual motorola 6.4 power dissipation note: these values are preliminary estimates. test values are tbd. characteristic symbol 5v typ 5v max unit normal mode at 20mhz pd(i) 70 tbd ma norlmal mode at 16mhz pd(i) 60 tbd ma low power standby mode pdsb(i) 7 tbd ma lo power doze mode pddz(i) 500 tbd m a low power stop mode pddz(i) 100 tbd m a
electrical characteristics motorola mc68lc302 reference manual 6-5 6.5 dc electrical characteristics note: the maximum i oh for a given pin is one-half the i ol rating for that pin. for an i oh between 400 m a and i ol /2 ma, the minimum v oh is calculated as: v dd - (1 +.05 v/ma(i oh -.400 ma)). characteristic symbol min max unit input high voltage (except pins noted below)) v ih 2.0 v dd v inputhighvoltage cd1 ,cts1 ,rxd1,txd1,rclk1,rts1 ,tclk1,pa7- pa10, pa12,cd2 , cts2 , rxd2, txd2, rclk2,rts2 , tclk2,tin1, tin2, tout2 , wdog ,pb8-pb11,reset (these pins have schmitt trigger inputs) v ih 2.5 v dd v input low voltage (except extal) v il v ss - 0.3 0.8 v input undershoot voltage v cil - -0.8 v input high voltage (extal) 3.3 volt or 5 volt part v cih .8 * v dd v dd v input low voltage (extal) v cil v ss - 0.3 0.6 v input leakage current ii n 20 m a input capacitance all pins c in 15 pf three-state leakage current (2.4/0.5 v) i tsi 20 m a open drain leakage current (2.4 v) i od 20 m a output high voltage (i oh = 400 m a) (see note) v oh v dd ?.0 v output low voltage (i o l = 3.2 ma) a1?19, pb3?b11, cs0?s3 bg , rclk1, rclk2, tclk1, tclk2, rts1 , rts2 , sds2, pa12, rxd2, cts2, cd2, (i o l = 5.3 ma) as , weh(uds ), wel(lds ), oe (r/w) bgack , dtack, d0?15, reset (i o l = 7.0 ma) txd1, txd2, (i ol = 8.9 ma) halt , br (as output) (i ol = 3.2 ma) clko v ol 0.5 0.5 0.5 0.5 0.4 v output drive clko output drive isdn i/f (gci mode) output drive all other pins o clk o gci o all 50 150 130 pf pf pf output drive derating factor for clko of 0.030 ns/pf output drive derating factor for clko of 0.025 ns/pf output drive derating factor for all other pins 0.025 ns/pf output drive derating factor for all other pins 0.05 ns/pf o kf o kf o kf o kf 20 50 20 100 50 130 100 200 pf pf pf pf power 5.0 volt part 3.3 volt part v dd 4.5 5.5 v 3.0 3.6 common v ss 0 0 v
electrical characteristics 6-6 mc68lc302 reference manual motorola 6.6 dc electrical characteristics?msi1 in idl mode 6.7 ac electrical specifications?lock timing (see figure 6-1) note: the minimum vco frequency and the pll default values put some restrictions on the minimum system frequency. figure 6-1. clock timing diagram characteristic symbol min max unit condition input pin characteristics: l1clk , l1sy1 , l1rxd , l1gr input low level voltage v il -10% + 20% v (% of v dd ) input high level voltage v ih v dd - 20% v dd + 10% v input low level current ii l 10 m a v in = v ss input high level current ii h 10 m a v in = v dd output pin characteristics: l1txd , sds1- sds2 , l1rq output low level voltage v ol 0 1.0 v i ol = 5.0 ma output high level voltage v oh v dd - 1.0 v dd v i oh = 400 m a 16.67 mhz 20 mhz 25 mhz num. characteristic symbol min max min max min max unit system frequency fsys dc 16.67 dc 20.00 dc 25.00 mhz crystal frequency f xtal 25 6000 25 6000 25 6000 khz on-chip vco system frequency fsys 10 16.67 10 20 10 25 mhz start-up time with external clock (oscillator disabled) or after changing the multiplication factor mf. with external crystal oscillator enabled. t pll t osc 2500 75,000 2500 75,000 2500 75,000 clks clko stability d clk tbd tbd tbd tbd tbd tbd % 1 clko period t cyc 60-50-40-ns 1a extal duty cycle t dcyc 40 60 40 60 40 60 % 1c external clock input period t extcyc 60-50-40-ns 2,3 clko pulse width (measured at 1.5v) t cw tbd - tbd - tbd - ns 4,5 clko rise and fall times (full drive) t crf -5-4-4ns 5b extal to clko skew (pll disabled) t extp 2112927ns extal clko (input) (output) 5 4 1 1c 2 3 5b voltage midpoint 1a
electrical characteristics motorola mc68lc302 reference manual 6-7 6.7.1 ac electrical characteristics - imp phased lock loop (pll) characteristics 1. f is the maximum operating frequency. ef is extal frequency. cxfc is the value of the pll capacitor (connected between xfc pin and vccsyn) for mf=1. the recommended value for c xfc is 400pf for mf < 5 and 540pf for mf> 5. the maximum vco frequency is limited to the internal operation frequency, as defined above. examples: 1. modck1,0 = 01; mf = 1 ?340 c xfc 480 pf 2. modck1,0 = 01; crystal is 32.768 khz (or 4.192 mhz), initial mf = 401, initial frequency = 13.14 mhz; later, mf is changed to 762 to support a frequency of 25 mhz. minimum c xfc is: 762 x 380 = 289 nf, maximum c xfc is: 401 x 970 = 390 nf. the recommended c xfc for 25 mhz is: 762 x 540 = 414 nf. 289 nf < c xfc < 390 nf and closer to 414 nf. the proper available value for c xfc is 390 nf. 3. modck1 pin = 1, crystal is 32.768 khz (or 4.192 mhz), initial mf = 401, initial frequency = 13.14 mhz; later, mf is changed to 1017 to support a frequency of 33.34 mhz. minimum c xfc is: 1017 x 380 = 386 nf. maximum c xfc is: 401 x 970 = 390 nf t 386 nf < c xfc < 390 nf. the proper available value for c xfc is 390 nf. 3a. in order to get higher range, higher crystal frequency can be used (i.e. 50 khz), in this case: minimum c xfc is: 667 x 380 = 253 nf. maximum c xfc is: 401 x 970 = 390 nf t 253 nf < c xfc < 390 nf. characteristics expression min max unit vco frequency when pll enabled mf * ef 10 f (note 1.) mhz pll external capacitor (xfc pin to vccsyn) mf * c xfc (note 1.) @ mf < 5 @ mf > 5 mf * 340 mf * 380 mf * 480 mf * 970 pf
electrical characteristics 6-8 mc68lc302 reference manual motorola 6.8 ac electrical specifications?mp bus master cycles (see figure 6-2, figure 6-3, and figure 6-4) num. characteristic symbol 16.67 mhz @5.0 v 20 mhz @5.0 v 25 mhz @5.0 v unit min max min max min max 6 clock high to fc, address valid t chfcadv 0 45 0 45 0 30 ns 7 clock high to address, data bus high im- pedance (maximum) t chadz 50 50 33 ns 8 clock high to address, fc invalid (mini- mum) t chafi 0 0 0 ns 9 clock high to as , ds asserted (see note 1) t chsl 3 30 3 30 3 20 ns 11 address, fc valid to as , ds asserted (read) as asserted write (see note 2) t afcvsl 15 15 10 ns 12 clock low to as , ds negated (see note 1) t clsh 30 30 20 ns 13 as , ds negated to address, fc invalid (see note 2) t shafi 15 15 10 ns 14 as (and ds read) width asserted (see note 2) t sl 120 120 80 ns 14a ds width asserted, write (see note 2) t dsl 60 60 40 ns 15 as , ds width negated (see note 2) t sh 60 60 40 ns 16 clock high to control bus high impedance t chcz 50 50 33 ns 17 as , ds negated to r/w invalid (see note 2) t shrh 15 15 10 ns 18 clock high to r/w high (see note 1) t chrh 30 30 20 ns 20 clock high to r/w low (see note 1) t chrl 30 30 20 ns 20a as asserted to r/w low (write) (see notes 2 and 6) t asrv 10 10 7 ns 21 address fc valid to r/w low (write) (see note 2) t afcvrl 15 15 10 ns 22 r/w low to ds asserted (write) (see note 2) t rlsl 30 30 20 ns 23 clock low to data-out valid t cldo 30 30 20 ns 25 as , ds , negated to data-out invalid (write) (see note 2) t shdoi 15 15 10 ns 26 data-out valid to ds asserted (write) (see note 2) t dosl 15 15 10 ns 27 data-in valid to clock low (setup time on read) (see note 5) t dicl 7 7 5 ns 28 as , ds negated to dtack negated (asyn- chronous hold) (see note 2) t shdah 0 110 0 110 0 75 ns 29 as , ds negated to data-in invalid (hold time on read) t shdii 0 0 ns 31 dtack asserted to data-in valid (setup time) (see notes 2 and 5) t daldi 50 50 33 ns 32 halt and reset input transition time t rhr , t rhf 150 150 150 ns 44 as , ds negated to avec negated t shvph 0 50 0 50 0 33 ns 47 asynchronous input setup time (see note 5) t asi 10 10 7 ns 53 data-out hold from clock high t chdoi 0 0 0 ns 55 r/w asserted to data bus impedance change t rldbd 0 0 0 ns
electrical characteristics motorola mc68lc302 reference manual 6-9 notes: 1. for loading capacitance of less than or equal to 50 pf, subtract 4 ns from the value given in the maximum columns. 2. actual value depends on clock period since signals are driven/latched on different clko edges. to calculate the actual spec for other clock frequencies, the user may derive the formula for each speci?ation. first, derive the margin factor as: m = n(p/2) - sa where n is the number of one-half clko periods between the two events as derived from the timing diagram, p is the rated clock period of the device for which the specs were derived (e.g., 60 ns with a 16.67-mhz device or 50 ns with a 20 mhz device), and sa is the actual spec in the data sheet. thus, for spec 14 at 16.67 mhz: m = 5(60 ns/2) - 120 ns = 30 ns. once the margin (m) is calculated for a given spec, a new value of that spec (sn) at another clock frequency with period (pa) is calculated as: sn = n(pa/2) - m thus for spec 14 at 12.5 mhz: sn = 5(80 ns/2) - 30 ns = 170 ns. these two formulas assume a 50% duty cycle. otherwise, if n is odd, the previous values n(p/2) and n(pa/2) must be reduced by x, where x is the difference between the nominal pulse width and the minimum pulse width of the extal input clock for that duty cycle. 4. for power-up, the mc68302 must be held in the reset state for 100 ms (or 2.3sec if mf=401) to allow stabilization of on-chip circuit. after the system is powered up #56 refers to the minimum pulse width required to reset the processor. 5. if the asynchronous input setup (#47) requirement is satis?d for dt ack , the dt ack asserted to data setup time (#31) requirement can be ignored. the data must only satisfy the data-in to clock low setup time (#27) for the following clock cycle. 6. when as and r/w are equally loaded ( 20%), subtract 5 ns from the values given in these columns. 56 halt /reset pulse width (see note 4) t hrpw 10 10 10 clks 61 clock high to bclr high impedance (see note 10) t chbch 30 30 20 ns
electrical characteristics 6-10 mc68lc302 reference manual motorola figure 6-2. read cycle timing diagram 8 6 7 15 9 11 14 12 17 18 28 29 47 32 56 47 32 47 data in halt / reset asynchronous inputs (note 1) s0 s1 s2 s3 s4 s5 s6 fc2?c0 a23?1 as lds?ds r/w dtack clko s7 27 13 notes: 1. setup time for the asynchronous inputs ipl2?pl0 guarantees their recognition at the next falling edge of the clock. 2. br need fall at this time only to insure being recognized at the end of the bus cycle. 3. timing measurements are referenced to and from a low voltage of 0.8 volt and a high voltage of 2.0 volts, unless otherwise noted. the voltage swing through this range should start outside and pass through the range such that the rise or fall is linear between 0.8 volts and 2.0 volts. cs, oe 47 178 31 175 150 174 173 176 152 151 171
electrical characteristics motorola mc68lc302 reference manual 6-11 figure 6-3. write cycle timing diagram 8 6 7 15 9 11 14 12 18 47 28 47 32 56 47 32 47 data out halt / reset asynchronous inputs (note 1) s0 s1 s2 s3 s4 s5 s6 fc2-fc0 a23-a1 as lds-uds, r/w dtack clko s7 20a 9 20 55 7 25 53 notes: 1. timing measurements are referenced to and from a low voltage of 0.8 volt and a high voltage of 2.0 volts, unless otherwise noted. the voltage swing through this range should start outside and pass through the 21 23 13 151 22 172 152 175 150 173 177 26 cs, 3. each wait state is a full clock cycle inserted between s4 and s5. 174 14a range such that the rise or fall is linear between between 0.8 volt and 2.0 volts. 2. because of loading variations, r/w may be valid after as even though both are initiated by the rising edge of s2 (specification #20a) 176 17 wel, weh 150
electrical characteristics 6-12 mc68lc302 reference manual motorola figure 6-4. read-modify-write cycle timing diagram clko s13 s14 s15 s16 s17 s18 s0 s1 s2 s3 s4 s5 s6 s7 s8 s12 s9 s10 s11 s19 12 9 9 12 9 18 data in 20 data out 23 25 29 27 18 indivisible cycle as (note 2) (output) uds?ds (output) dtack d15?0 r/w (output) as (note 3) (output)
electrical characteristics motorola mc68lc302 reference manual 6-13 6.9 ac electrical specifications?ma (see figure 6-5 and figure 6-6) notes: 1. br will not be asserted while as , hal t , or berr is asserted. 2. speci?ations are for disable cpu mode only. 3. dma and sdma read and write cycle timing is the same as that for the m68000 core. num. characteristic symbol 16.67 mhz 20 mhz 25 mhz unit min max min max min max 83 clock high to br low (see notes 3 and 4) t chbrl 30 25 20 ns 84 clock high to br high impedance (see notes 3 and 4) t chbrz 30 25 20 ns 85 bgack low to br high impedance (see notes 3 and 4) t bklbrz 30 25 20 ns 86 clock high to bgack low t chbkl 30 25 20 ns 87 as and bgack high (the latest one) to b gack low (when bg is asserted) t abhbkl 1.5 2.5 +30 1.5 2.5 +25 1.5 2.5 +20 clks ns 88 bg low to bgack low (no other bus master) (see notes 3 and 4) t bglbkl 1.5 2.5 +30 1.5 2.5 +25 1.5 2.5 +20 clks ns 89 br high impedance to bg high (see notes 3 and 4) t brhbgh 0 0 0 ns 90 clock on which bgack low to clock on which as low t clbklal 2 2 2 2 2 2 clks 91 clock high to bgack high t chbkh 30 25 20 ns 92 clock low to bgack high impedance t clbkz 15 15 10 ns
electrical characteristics 6-14 mc68lc302 reference manual motorola figure 6-5. dma timing diagram (idma) notes: 1. br and bg shown above are only active in disable cpu mode; otherwise, they do not apply to the diagram. (output) bgack (i/o) as clko (output) br (input) bg (output) r/w note 1 note 1 s0 s1 s2 s3 s4 s5 s6 s7 92 91 90 87 88 86 81 80 47 89 83 82 85 see m68000 read cycles for additional bus signals and timing. s0 s1 s2 s3 s4 s5 s6 s7 see m68000 write cycles for additional bus signals and timing. 84
electrical characteristics motorola mc68lc302 reference manual 6-15 figure 6-6. dma timing diagram (sdma) (output) bgack (i/o) as clko (output) br (input) bg (note 2) (note 2) s0 s1 s2 s3 s4 s5 s6 s7 92 91 90 87 88 47 89 83 85 see m68000 read/write cycles for additional bus signals and timing. 6 86 notes: 1. dram refresh controller timing is identical to sdma timing. 2. br and bg shown above are only active in disable cpu mode; otherwise they do not apply to the diagram.
electrical characteristics 6-16 mc68lc302 reference manual motorola 6.10 ac electrical specifications?xternal master internal asynchronous read/write cycles (see figure 6-7 and figure 6-8) note: if as is negated before ds , the data bus could be three-stated (spec 126) before ds is negated. num. characteristic symbol 16.67 mhz 20 mhz 25 mhz unit min max min max min max 100 r/w valid to ds low t rwvdsl 0 0 0 ns 101 ds low to data-in valid t dsldiv 30 25 20 ns 102 dtack low to data-in hold time t dkldh 0 0 0 ns 103 as valid to ds low t asvdsl 0 0 0 ns 104 dtack low to as , ds high t dkldsh 0 0 0 ns 105 ds high to dtack high t dshdkh 45 40 30 ns 106 ds inactive to as inactive t dsiasi 0 0 0 ns 107 ds high to r/w high t dshrwh 0 0 0 ns 108 ds high to data high impedance t dshdz 45 40 30 ns 108a ds high to data-out hold time (see note) t dshdh 0 0 0 ns 109a data out valid to dtack low t dovdkl 15 15 10 ns
electrical characteristics motorola mc68lc302 reference manual 6-17 figure 6-7. external master internal asynchronous read cycle timing diagram s0 s1 s2 s3 sw s5 s6 s7 s0 sw sw sw sw sw s4 clko (output) a23-a1 (input) iac (output) d15-d0 (output) as (input) r/w (input) 128 106 114 110 103 129 119 104 120 108 108a 125 122 109a 124 105 47 dtack (output) (input) uds lds
electrical characteristics 6-18 mc68lc302 reference manual motorola figure 6-8. external master internal asynchronous write cycle timing diagram s0 s1 s2 s3 s4 s5 s6 s7 sw sw sw sw sw s4 clko (output) a23-a1 (input) iac (output) d15-d0 (input) as (input) r/w (input) 113 114 110 129 119 104 120 102 101 122 124 105 47 dtack (output) 100 103 107 (input) uds lds
electrical characteristics motorola mc68lc302 reference manual 6-19 6.11 ac electrical specifications?xternal master internal synchronous read/write cycles (see figure 6-9, figure 6-10, and figure 6-11) notes: 1. synchronous speci?ations above are valid only when sam = 1 in the scr. 2. it is required that this signal not be asserted prior to the previous rising clko edge (i.e., in the previous clock cycle). it must be recognized by the imp no sooner than the rising clko edge shown in the diagram. num. characteristic symbol 16.67 mhz 20 mhz 25 mhz unit min max min max min max 110 address valid to as low t avasl 15 12 10 ns 111 as low to clock high t aslch 30 25 20 ns 112 clock low to as high t clash 45 40 30 ns 113 as high to address hold time on write t ashah 0 0 0 ns 114 as inactive time t ash 1 1 1 clk 115 uds /lds low to clock high (see note 2) t slch 40 33 27 ns 116 clock low to uds /lds high t clsh 45 40 30 ns 117 r/w valid to clock high (see note 2) t rwvch 30 25 20 ns 118 clock high to r/w high t chrwh 45 40 30 ns 119 as low to iac high t asliah 40 35 27 ns 120 as high to iac low t ashial 40 35 27 ns 121 as low to dtack low (0 wait state) t asldtl 45 40 30 ns 122 clock low to dtack low (1 wait state) t cldtl 30 25 20 ns 123 as high to dtack high t ashdth 45 40 30 ns 124 dtack high to dtack high impedance t dthdtz 15 15 10 ns 125 clock high to data-out valid t chdov 30 25 20 ns 126 as high to data high impedance t ashdz 45 40 30 ns 127 as high to data-out hold time t ashdoi 0 0 0 ns 128 as high to address hold time on read t ashai 0 0 0 ns 129 uds /lds inactive time t sh 1 1 1 clk 130 data-in valid to clock low t cldiv 30 25 20 ns 131 clock low to data-in hold time t cldih 15 12 10 ns
electrical characteristics 6-20 mc68lc302 reference manual motorola figure 6-9. external master internal synchronous read cycle timing diagram (output) (output) 110 114 129 116 120 112 128 111 119 115 125 127 126 121 123 124 a23-a1 (input) iac (output) lds uds (input) d15?0 as (input) r/w (input) dtack (output) s0 s1 s2 s3 s4 s5 s6 s7 s0 clko
electrical characteristics motorola mc68lc302 reference manual 6-21 figure 6-10. external master internal synchronous read cycle timing diagram (one wait state) a23?1 clko (output) (input) iac (output) as (input) 119 120 112 s0 s1 s2 s3 sw s5 s6 s7 s0 s4 sw 111 128 110 lds uds (input) r/w (input) dtack (output) d15?0 (output) 116 123 124 127 126 125 115 129 114 122
electrical characteristics 6-22 mc68lc302 reference manual motorola figure 6-11. external master internal synchronous write cycle timing diagram s0 s1 s2 s3 s4 s5 s6 s7 s0 as iac (output) 110 111 119 114 113 112 120 a23?1 clko 115 116 uds lds (input) (input) r/w d0?15 (input) 117 130 131 dtack 123 124 121 (input) (input) 129 (output) 118
electrical characteristics motorola mc68lc302 reference manual 6-23 6.12 ac electrical specifications?nternal master internal read/write cycles ( see figure 6-12 ) figure 6-12. internal master internal read cycle timing diagram num. characteristic symbol 16.67 mhz 20 mhz 25 mhz unit min max min max min max 140 clock high to iac high t chiah 40 35 27 ns 141 clock low to iac low t clial 40 35 27 ns 142 clock high to dtack low t chdtl 45 40 30 ns 143 clock low to dtack high t cldth 40 35 27 ns 144 clock high to data-out valid t chdov 30 25 20 ns 145 as high to data-out hold time t ashdoh 0 0 0 ns as (output) (output) iac (output) 140 141 r/w (output) d15-d0 145 144 (output) dtack (output) 143 142 lds uds (output) a23-a1 (output) clko s0 s1 s2 s3 s4 s5 s6 s7 s0
electrical characteristics 6-24 mc68lc302 reference manual motorola 6.13 ac electrical specifications?hip-select timing internal master (see figure 6-13 ) note: 1. this speci?ation is valid only when the adce or wpve bits in the scr are set. 2.for loading capacitance less than or equal to 50 pf, subtract 4 ns from the maximum value given. 3. since as and cs are asserted/negated on the same clko edges, no as to cs relative timings can be speci?d. however, cs timings are given relative to a number of other signals, in the same manner as as. see figure 6-2 and figure 6-3 for diagrams. figure 6-13. internal master chip-select timing diagram num. characteristic symbol 16.67 mhz 20 mhz 25 mhz unit min max min max min max 150 clock high to cs , iack , oe , wel , weh low (see note 2) t chcsiakl 0 40 0 35 0 27 ns 151 clock low to cs , iack , oe , wel , weh high (see note 2) t clcsiakh 0 40 0 35 0 27 ns 152 cs width negated t csh 60 50 40 ns 153 clock high to dtack low (0 wait state) t chdtkl 45 40 30 ns 154 clock low to dtack low (1? wait states) t cldtkl 30 25 20 ns 155 clock low to dtack high t cldtkh 40 35 27 ns 158 dtack high to dtack high impedance t dtkhdtkz 15 15 27 ns 171 input data hold time from s6 low t idhcl 5 5 27 ns 172 cs negated to data-out invalid (write) t csndoi 10 10 10 ns 173 address, fc valid to cs asserted t afvcsa 15 15 5 ns 174 cs negated to address, fc invalid t csnafi 15 15 7 ns 175 cs low time (0 wait states) t cslt 120 100 15 ns 176 cs negated to r/w invalid t csnrwi 10 10 12 ns 177 cs asserted to r/w low (write) t csarwl 10 10 80 ns 178 cs negated to data-in invalid (hold time on read) t csndii 0 0 7 ns clko (output) (output) iack1,iack6, cs0?s3 iack7 dtack (output) 150 151 152 sw sw s5 s6 s7 s0 s0 s1 s2 s3 s4 s5 s6 s7 s0 s4 153 155 158 154 s1 s2 s3
electrical characteristics motorola mc68lc302 reference manual 6-25 6.14 ac electrical specifications?hip-select timing external master (see figure 6-14) figure 6-14. external master chip-select timing diagram num. characteristic symbol 16.67 mhz 20 mhz 25 mhz unit min max min max min max 154 clock low to dtack low (1-6 wait states) t cldtkl 30 25 20 ns 160 as low to cs low t aslcsl 30 25 20 ns 161 as high to cs high t ashcsh 30 25 20 ns 162 address valid to as low t avasl 15 12 10 ns 164 as negated to address hold time t ashai 0 0 0 ns 165 as low to dtack low (0 wait state) t asldtkl 45 40 30 ns 167 as high to dtack high t ashdtkh 30 25 20 ns a23-a1 (input) dtack (output) r/w (input) berr (output) clko s0 s1 s2 s3 s4 s5 s6 s7 s0 cs3-cs0, 165 158 169 161 167 164 168 162 as (input) 163 oe 160 weh, wel, (output) 150
electrical characteristics 6-26 mc68lc302 reference manual motorola 6.15 ac electrical specifications?arallel i/o (see figure 6-15 ) figure 6-15. parallel i/o data-in/data-out timing diagram 6.16 ac electrical specifications?nterrupts (see figure 6-16 ) note: setup time for the asynchronous inputs ipl2?pl0 and a vec guarantees their recognition at the next falling edge of the clock. num. characteristic symbol 16.67 mhz 20 mhz 25 mhz unit min max min max min max 180 input data setup time (to clock low) t dsu 20 20 14 ns 181 input data hold time (from clock low) t dh 10 10 19 ns 182 clock high to data-out valid (cpu writes data, control, or direction) t chdov 35 30 24 ns num. characteristic symbol 16.67 mhz 20 mhz 25 mhz unit min max min max min max 190 interrupt pulse width low irq (edge trig- gered mode) t ipw 50 42 34 ns 191 minimum time between active edges t aemt 3 3 3 clk data out data in 181 cpu write (s6) of port data, control, or direction register 182 clko 180
electrical characteristics motorola mc68lc302 reference manual 6-27 figure 6-16. interrupts timing diagram irq (input) 191 190
electrical characteristics 6-28 mc68lc302 reference manual motorola 6.17 ac electrical specifications?imers note: the frz pin is not implemented on the lc302. (see figure 6-17) notes: 1. frz should be negated during total system reset. 2. the tin specs above do not apply to the use of tin1 as a baud rate generator input clock. in such a case, speci?ations 1? may be used. figure 6-17. timers timing diagram num. characteristic symbol 16.67 mhz 20 mhz 25 mhz unit min max min max min max 200 timer input capture pulse width t tpw 50 42 34 ns 201 tin clock low pulse width t ticlt 50 42 34 ns 202 tin clock high pulse width and input capture high pulse width t ticht 2 2 2 clk 203 tin clock cycle time t cyc 3 3 3 clk 204 clock high to tout valid t chtov 35 30 24 ns 205 frz input setup time (to clock high) (see note 1) t frzsu 20 20 14 ns 206 frz input hold time (from clock high) t frzht 10 10 7 ns clko 204 202 201 203 tin (input) tout (output) 206 205 frz (input) 200
electrical characteristics motorola mc68lc302 reference manual 6-29 6.18 ac electrical specifications?erial communications port (see figure 6-18 ). notes: 1. this also applies when spclk is inverted by ci in the spmode register. 2. the enable signals for the slaves may be implemented by the parallel i/o pins. figure 6-18. serial communication port timing diagram num. characteristic 16.67 mhz 20 mhz 25 mhz unit min max min max min max 250 spclk clock output period 4 64 4 64 4 64 clks 251 spclk clock output rise/fall time 0 15 0 10 0 8 ns 252 delay from spclk to transmit (see note 1) 0 40 0 30 0 24 ns 253 scp receive setup time (see note 1) 40 30 24 ns 254 scp receive hold time (see note 1) 10 8 7 ns 1234 567 8 12 3 45 6 78 spclk (output) sptxd (output) sprxd (input) 250 252 251 253 254
electrical characteristics 6-30 mc68lc302 reference manual motorola 6.19 ac electrical specifications?dl timing (all timing measurements , unless otherwise specified , are referenced to the l1clk at 50% point of v dd ) (see figure 6-19 ) notes: 1. the ratio clko/l1clk must be greater than 2.5/1. 2. high impedance is measured at the 30% and 70% of v dd points, with the line at v dd /2 through 10k in parallel with 130 pf. 3. where p = 1/clko. thus, for a 16.67-mhz clko rate, p = 60 ns. num. characteristic 16.67 mhz 20 mhz 25 mhz unit min max min max min max 260 l1clk (idl clock) frequency (see note 1) 6.66 8 10 mhz 261 l1clk width low 55 45 37 ns 262 l1clk width high (see note 3) p+10 p+10 p+10 ns 263 l1txd, l1rq, sds1?ds2 rising/falling time 20 17 14 ns 264 l1sy1 (sync) setup time (to l1clk falling edge) 30 25 20 ns 265 l1sy1 (sync) hold time (from l1clk fall- ing edge) 50 40 34 ns 266 l1sy1 (sync) inactive before 4th l1clk 0 0 0 ns 267 l1txd active delay (from l1clk rising edge) 0 75 0 65 0 50 ns 268 l1txd to high impedance (from l1clk ris- ing edge) (see note 2) 0 50 0 42 0 34 ns 269 l1rxd setup time (to l1clk falling edge) 50 42 34 ns 270 l1rxd hold time (from l1clk falling edge) 50 42 34 ns 271 time between successive idl syncs 20 20 20 l1clk 272 l1rq valid before falling edge of l1sy1 1 1 1 l1clk 273 l1gr setup time (to l1sy1 falling edge) 50 42 34 ns 274 l1gr hold time (from l1sy1 falling edge) 50 42 34 ns 275 sds1?ds2 active delay from l1clk ris- ing edge 10 75 10 65 7 50 ns 276 sds1?ds2 inactive delay from l1clk falling edge 10 75 10 65 7 50 ns
electrical characteristics motorola mc68lc302 reference manual 6-31 figure 6-19. idl timing diagram (output) l1clk (input) l1rxd l1sy1 (input) sds1?ds2 (output) l1txd l1rq (output) l1gr (input) 265 261 263 272 268 (input) 273 269 267 264 270 260 10 11 12 13 16 17 18 14 15 19 b10 276 d1 b10 b11 a b27 b26 b25 b24 b23 b22 b21 b20 d2 m b17 b15 b14 b12 b13 b16 68 12 3 45 7 9 20 d1 b11 a b27 b26 b25 b24 b23 b22 b21 b20 d2 m b17 b15 b14 b12 b13 b16 275 262 266 271 274
electrical characteristics 6-32 mc68lc302 reference manual motorola 6.20 ac electrical specifications?ci timing gci supports the normal mode and the gci channel 0 (gcn0) in mux mode. normal mode uses 512 khz clock rate (256k bit rate). mux mode uses 256 x n - 3088 kbs (clock rate is data rate x 2). the ratio clko/l1clk must be greater than 2.5/1 (see figure 6-20). notes: 1. the ratio clko/l1clk must be greater than 2.5/1. 2. condition c l = 150 pf. l1td becomes valid after the l1clk rising edge or l1sy1, whichever is later. 3. sds1?ds2 become valid after the l1clk rising edge or l1sy1, whichever is later. 4. schmitt trigger used on input buffer. 5. where p = 1/clko. thus, for a 16.67-mhz clko rate, p = 60 ns. num. characteristic 16.67 mhz 20 mhz 25 mhz unit min max min max min max l1clk gci clock frequency (normal mode) (see note 1) 512 512 512 khz 280 l1clk clock period normal mode (see note 1) 1800 2100 1800 2100 1800 2100 ns 281 l1clk width low/high normal mode 840 1450 840 1450 840 1450 ns 282 l1clk rise/fall time normal mode (see note 4) ns l1clk (gci clock) period (mux mode) (see note 1) 6.668 6.668 6.668 mhz 280 l1clk clock period mux mode (see note 1) 150 150 150 ns 281 l1clk width low mux mode 55 55 55 ns 281a l1clk width high mux mode (see note 5) p+10 p+10 p+10 ns 282 l1clk rise/fall time mux mode (see note 4) ns 283 l1sy1 sync setup time to l1clk falling edge 30 25 20 ns 284 l1sy1 sync hold time from l1clk falling edge 50 42 34 ns 285 l1txd active delay (from l1clk rising edge) (see note 2) 0 100 0 85 0 70 ns 286 l1txd active delay (from l1sy1 rising edge) (see note 2) 0 100 0 85 0 70 ns 287 l1rxd setup time to l1clk rising edge 20 17 14 ns 288 l1rxd hold time from l1clk rising edge 50 42 34 ns 289 time between successive l1sy1in normal scit mode 64 192 64 192 64 192 l1clk l1clk 290 sds1?ds2 active delay from l1clk rising edge (see note 3) 10 90 10 75 7 60 ns 291 sds1?ds2 active delay from l1sy1 rising edge (see note 3) 10 90 10 75 7 60 ns 292 sds1?ds2 inactive delay from l1clk falling edge 10 90 10 75 7 60 ns 293 gcidcl (gci data clock) active delay 0 50 0 42 0 34 ns
electrical characteristics motorola mc68lc302 reference manual 6-33 figure 6-20. gci timing diagram l1clk (input) l1sy1 (input) sds1?ds2 (output) gcidcl (output) l1txd (output) l1rxd (input) 291 285 284 280 282 281 289 292 293 288 290 286 283 287
electrical characteristics 6-34 mc68lc302 reference manual motorola 6.21 ac electrical specifications?cm timing there are two sync types: short frame?ync signals are one clock cycle prior to the data long frame?ync signals are n-bits that envelope the data , n > 0; see figure 6-21 and figure 6-22). notes: 1. the ratio clk/l1clk must be greater than 2.5/1. 2. l1txd becomes valid after the l1clk rising edge or the sync enable, whichever is later, if long frames are used. 3. speci?ation valid for both sync methods. 4. where p = 1/clko. thus, for a 16.67-mhz clko rate, p = 60 ns. num. characteristic 16.67 mhz 20 mhz 25 mhz unit min max min max min max 300 l1clk (pcm clock) frequency (see note 1) 6.66 8.0 10.0 mhz 301 l1clk width low 55 45 37 ns 301a l1clk width high (see note 4) p+10 p+10 p+10 ns 302 l1sy0?1sy1 setup time to l1clk rising edge 0 0 0 ns 303 l1sy0?1sy1 hold time from l1clk falling edge 40 33 27 ns 304 l1sy0?1sy1 width low 1 1 1 l1clk 305 time between successive sync signals (short frame) 8 8 8 l1clk 306 l1txd data valid after l1clk rising edge (see note 2) 0 70 0 60 0 47 ns 307 l1txd to high impedance (from l1clk rising edge) 0 50 0 42 0 34 ns 308 l1rxd setup time (to l1clk falling edge) (see note 3) 20 17 14 ns 309 l1rxd hold time (from l1clk falling edge) (see note 3) 50 42 34 ns
electrical characteristics motorola mc68lc302 reference manual 6-35 figure 6-21. pcm timing diagram (sync envelopes data) figure 6-22. pcm timing diagram (sync prior to 8-bit data) l1clk (input) l1sy0/1 (input) l1txd (output) l1rxd (input) 1 23 5 n-1 n 12 3 4 n-1 n 1 n-1 n 23 306 307 303 302 302 308 309 l1clk (input) l1sy0/1 (input) l1txd (output) l1rxd (input) note: (*) if l1syn is guaranteed to make a smooth low to high transition (no spikes) while the clock is high, setup time can be defined as shown (min 20 ns). 1 2 3 56 78 8 4 5 6 7 302 304 305 306 307 4 8 1 23 5 6 7 308 309 303 (*) 4 12 3
electrical characteristics 6-36 mc68lc302 reference manual motorola 6.22 ac electrical specifications?msi timing the nmsi mode uses two clocks , one for receive and one for transmit. both clocks can be internal or external. when t he clock is internal , it is generated by the internal baud rate gen- erator and it is output on tclk or rclk. all the timing is related to the external clock pin. the timing is specified for nmsi1. it is also valid for nmsi2 and nmsi3 (see figure 6-23). notes: 1. the ratio clko/tclk1 and clko/rclk1 must be greater than or equal to 2.5/1 for external clock. the input clock to the baud rate generator may be either an internal clock or tin1, and may be as fast as extal. however, the output of the baud rate generator must provide a clko/tclk1 a nd clko/rclk1 ratio greater than or equal to 3/1.in asynchronous mode (uart), the bit rate is 1/16 of the tclk1/rclk1 clock rate. 2. also applies to cd hold time when cd is used as an external sync in bisync or totally transparent mode. 3. schmitt triggers used on input buffers. 4. where p = 1/clko. thus, for a 16.67-mhz clko rate, p = 60 ns. num. characteristic 16.67 mhz 16.67 mhz 20 mhz 20 mhz 25 mhz 25 mhz unit internal clock external clock internal clock external clock internal clock external clock min max min max min max min max min max min max 315 rclk1 and tclk1 fre- quency (see note 1) 5.55 6.668 6.66 8 8.33 10 mhz 316 rclk1 and tclk1 low (see note 4) 65 p+10 55 p+10 45 p+10 ns 316a rclk1 and tclk1 high 65 55 55 45 45 35 ns 317 rclk1 and tclk1 rise/fall time (see note 3) 20 17 14 ns 318 txd1 active delay from tclk1 falling edge 0 40 0 70 0 30 0 50 0 25 0 40 ns 319 rts1 active/inactive delay from tclk1 falling edge 0 40 0 100 0 30 0 80 0 25 0 65 ns 320 cts1 setup time to tclk1 rising edge 50 10 40 7 35 7 ns 321 rxd1 setup time to rclk1 rising edge 50 10 40 7 35 7 ns 322 rxd1 hold time from rclk1 rising edge (see note 2) 10 50 7 40 7 35 ns 323 cd1 setup time to rclk1 rising edge 50 10 40 7 35 7 ns
electrical characteristics motorola mc68lc302 reference manual 6-37 figure 6-23. nmsi timing diagram rxd1 (input) rclk1 323 322 321 317 317 315 316 cd1 (input) 322 cd1 (sync input) txd1 (output) tclk1 319 318 315 316 317 317 320 cts1 (input) rts1 (output) 319
electrical characteristics 6-38 mc68lc302 reference manual motorola
motorola mc68lc302 user? manual supplement 7-1 section 7 mechanical data and ordering information 7.1 pin assignments 7.1.1 pin grid array (pga) a b c d e f g h j k l m n 12345678910111213 mc68lc302rc bottom view pb11 cs0 iac a1 a2 a3 a4 gnda2 fc2 a8 a9 a10 a11 a15 a5 nc pb8 cs3 cs1 gnda3 fc1 a6 vcca1 a12 a14 a19 d13 tin1 wdog pb9 cs2 vcca2 fc0 a7 vcca1 a13 a18 gndq3 d12 nc wel tn2 tout2 pb10 a16 gnda1 d15 d14 d10 gndp2 weh vccp1 gndp a17 gndd1 d11 d9 vccq1 oe as nc nc d8 gndq1 vccq1 gndq1 gndq2 vccq2 nc ipl0 ipl1 ipl2 nc gndq2 vccd1 extal xtal nc nc rxd1 d5 d6 nc frz discpu busw halt cd1 d3 gndd2 d7 vccsyn pa8 pa7 xfc gndsyn nc nc avec rts2 gnds1 rxd2 d0 d2 d4 tclk1 clko nc reset dtack pa10 vccs1 cd2 nc txd2 pa9 d1 gndq4 txd1 nc nc rts1 gnds2 rclk1 vccq3 nc cts2 tclk2 nc rclk2 cts1 pa12
mechanical data and ordering information 7-2 mc68lc302 user? manual supplement motorola 7.1.2 surface mount (tqfp ) 1 25 100 26 50 51 75 76 pb09 halt reset dtack txd2 pa10 rts1 gnds2 cd1 rclk1 tclk1 txd1 vccs1 pa12 pa7 cd2 rts2 cts2 tclk2 gnds1 rclk2 rxd2 pa9 rxd1 pa8 cts1 gndp gndp pb10 pb11 a10 cs2 cs3 cs1 gnda1 cs0 a1 a2 a4 a3 a5 gnda2 a6 a7 a8 a9 vcca1 a11 a12 a14 a13 a15 pb08 tin2 tout2 wdog tin1 vccp1 gndp2 (lds)wel (uds)weh as (r/w)oe (br) ipl0 gndq1 vccq1 (bgack)ipl1 extal discpu clk0 xtal busw vccsyn xfc gndsyn (bg) ipl2 a16 a17 d15 a19 a18 d14 d13 d11 gndd1 d12 d10 d9 gndq2 vccq2 d8 d7 d4 d5 d6 gndd2 d0 d1 d3 vccd1 d2 mc68lc302pu top view
mechanical data and ordering information motorola mc68lc302 user? manual supplement 7-3 7.2 package dimensions 7.2.1 pin grid array (pga) c k 1 2 3 4 5 6 7 8 9 10 11 12 13 a b c d e f g h k l m n j g g mc68ec030 rp suffix package case 789b-01 a b t notes: 1. a and b are datums and t is a datum surface. 2. positional tolerance for leads (132 pl). 3. dimensioning and tolerancing per y14.5m,1982. 4. controlling dimension: inch. 0d 0.13 (0.005) m t a s b s f dim millimeters inches min max min max a b c d g 1.340 1.380 1.340 1.380 0.100 0.150 34.04 35.05 34.04 35.05 2.54 3.81 0.43 0.55 0.017 0.022 0.100 bsc 2.54 bsc k 4.32 4.95 0.170 0.195
mechanical data and ordering information 7-4 mc68lc302 user? manual supplement motorola 7.2.2 surface mount (tqfp) case 983-01 issue a date 07/14/94 !($
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mechanical data and ordering information motorola mc68lc302 user? manual supplement 7-5 7.3 ordering information package type frequency (mhz) temperature order number pin grid array (rc suffix) 16.67 16.67 20 20 0 c to 70 c - 40 c to + 85 c 0 c to 70 c - 40 c to + 85 c mc68lc302rc16 mc68lc302crc16 mc68lc302rc20 mc68lc302crc20 surface mount (pu suffix) 16.67 20 0 c to 70 c 0 c to 70 c MC68LC302PU16 mc68lc302pu20
mechanical data and ordering information 7-6 mc68lc302 user? manual supplement motorola
motorola mc68lc302 reference manual index-1 index a address as 3-25 decode conflict 2-4 decode conflict 3-3, 3-4 address bus pins 5-7 as 3-3, 3-25, 5-9 at command set 4-9 autobaud controller 4-9 autobaud command descriptor 4-14 autobaud lookup table format 4-16 autobaud parameter ram 4-11 autobaud sampling rate 4-15 autobaud transmission 4-18 automatic echo 4-19 carrier detect lost 4-18 channel reception process 4-9 determining character length and parity 4-17 end of table error 4-18 enter_baud_hunt command 4-14 lookup table 4-15 lookup table example 4-17 lookup table pointer 4-15 lookup table size 4-15 maximum start bit length 4-16 overrun error 4-18 performance 4-9 preparing for the autobaud process 4-13 programming model 4-13 reception error handling procedure 4- 18 reprogramming to uart mode or another protocol 4-20 smart echo 4-11, 4-19 smart echo hardware setup 4-11 start bit 4-9 transmit process 4-11 automatic echo 4-5 b base address regisrter 2-4 baud rate generator 5-18 bcr 3-13 berr 2-4, 3-3, 3-4, 3-5, 3-6 berr see signals bg 3-28, 5-11 bgack 5-11 bisync controller 4-22 bisync event register 4-23 bisync mask register 4-23 bisync memory map 4-22 bisync mode register 4-22 bisync receive buffer descriptor 4-22 bisync transmit buffer descriptor 4-22 bootstrap 3-7 br 3-28, 3-29, 5-10 br3?r0 3-26 brg 2-12 brg clock 2-12 brg divide by two system clock 2-14 bsr 3-6 buffer buffer descriptor 4-6 descriptors 2-20, 3-29 buffer descriptor 4-6 buffer descriptors table 4-6 bus arbitration 3-28, 5-11 bandwidth 3-12 error 2-4 grant (bg) 5-11 grant acknowledge (bgack) 5-11 master 3-28 request (br) 5-10 signal summary 5-13 bus arbitration logic 3-28 external bus arbitration 3-28 internal bus arbitration 3-28
index index-2 mc68lc302 reference manual motorola bus arbitration pins 5-10 bus control pins 5-9 bus states during low power modes 68000 2-15 busw 2-1, 5-7 c changes to imp clko drive options 2-6 three-state tclk1 2-6 three-state rclk1 2-6 chip-select 2-4 as 3-25 base address 3-27 base register 3-26 cs0 3-26, 3-28, 5-21 dtack 3-26 option register 3-26 chip-select pins 5-21 chip-select registers 3-26 chip-select timing 6-24 clko output buffer strength 2-11 clkomod1? 2-6 clock clko 5-4 clock pins 5-4 cmos level 5-2 cmr 3-11 communications processor 4-1 configuration mc68302 imp control 2-3 cqfp 7-2 crystal oscillator 2-8 crystal oscillator circuit (imp) 2-9 cs0 3-26, 3-28, 5-21 cs1 2-23, 2-24, 5-21 cs2 2-23, 2-24 cs3 2-23, 3-26, 5-1, 5-10, 5-21 cs3?s1 5-21 cselect 2-7 csr 3-13 d dapr 3-13 data bus pins 5-8 default system clock generation 2-7 df0? 2-10 disable cpu 5-7 bg 3-28 br 3-28 cs0 3-28 dtack 3-28 emws 3-28 sam 3-28 disable cpu logic 3-28 disable scc1 serial clocks out 4-4 disc 4-4 discpu 3-28, 5-7 divide by two block from tin1 pin 4-5 dma control 3-10 doze 2-13, 2-16 dram refresh buffer descriptors 3-29 pb8 3-18 drive 2-13 dsr 4-6 dtack 3-4, 3-26, 3-28, 5-10, 5-12 dynamic ram refresh controller 3-29 e emws (external master wait state) 3-4, 3-5, 3-28 enable receiver 4-5 enable transmitter 4-6 exception pb8 3-29 extal 5-2, 5-4 external bus master 3-28 external bus arbitration using halt 3-28 master wait state (emws) 3-5 external bus arbitration 3-28 external master wait state 3-4 f fcr 3-13 freeze control 3-5 frz 5-7 function codes 3-13, 5-12 comparison 2-4 fc2-fc0 2-4, 5-12 register 3-13
index motorola mc68lc302 reference manual index-3 g gci 4-2, 5-14, 5-15 scit 4-2 simask 4-4 simode 4-2 gci see signals gimr 3-14 gndsyn 2-12, 5-5 h halt 2-4, 5-6 halt see signals hardware watchdog 3-5 berr 3-5, 3-6 hdlc hdlc event register 4-21 hdlc mask register 4-21 hdlc memory map 4-20 hdlc mode register 4-20 rx bd 4-21 scce 4-21 sccm 4-21 tx bd 4-21 hdlc controller 4-20 hdlc event register 4-21 hdlc mask register 4-21 hdlc memory map 4-20 hdlc mode register 4-20 hdlc receive buffer descriptor 4-21 hdlc transmit buffer descriptor 4-21 i iac 5-10 idl 4-2, 5-14, 5-15 simask 4-4 simode 4-2 idl see signals idma (independent dma controller) dreq 3-11 imp features cp 1-2 imp operation mode control register (iomcr) 2-14, 2-15 imp pll and clock control register (iplcr) 2-10 imp pll pins 2-12 gndsyn 2-12 modclk 2-12 vccsyn 2-12 xfc 2-12 imp system clock generation iomcr 2-8, 2-9, 2-10 iplcr 2-8, 2-10 imp system clocks schematic pll disabled 2-8 imp wake-up from low power stop modes 2-17 imr 3-16 internal loopback 4-3 internal registers 2-22 internal registers map 2-23 interrupt acknowledge 2-4 control pins 5-11 controller 3-14 ipr 3-15 isr 3-16 interrupt control pins 5-11 interrupt controller 3-14 iomcr 2-7, 2-14, 2-16 ipl 5-11 ipl0 5-11 ipl1 5-11 ipl2 5-11 ipl2-ipl0 5-11 iplcr 2-7, 2-10 ipr 3-15 ipwrd 2-15 irq1 5-12 isdn 5-14 isr 3-16 iwucr 2-17 l loopback control 4-3 loopback mode internal loopback 4-3 loopback control 4-3 loopback mode 4-5 low power 2-13 68000 bus 2-13 low power drive control register 2-13 low power drive control register (lpdcr)
index index-4 mc68lc302 reference manual motorola 2-15 low power modes imp 2-13 low power support 2-15 fast wake-up 2-18 stop/ doze/ stand_by mode 2-16 wake-up from low power stop modes 2-17 low-power clock divider 2-9 lpdcr 2-15 lpm1? 2-15 m mc68000/mc68008 modes 2-1 mc68lc302 system clock generation iomcr 2-6 iplcr 2-6 iwucr 2-6 modclk 2-7 pitr 2-6 vccsyn 2-7 mf 11? 2-11 modclk 2-12 modclk/pa12 5-5 modclk1? 2-7 multiplication factor 2-11 n nmsi 4-2, 5-14 cd1 5-16 cts1 5-17 nmsi1 5-15 nmsi2 5-17 nmsi3 5-18 rts1 5-17 simode 4-2 nmsi1 or isdn interface pins 5-14 nmsi2 port or port a pins 5-17 normal operation 4-5 o oe (r/w) 5-9 or3?r0 3-26 oscillator 2-8 p pacnt 3-19 paddr 3-19 paio / scp pins 5-18 parallel 5-20 parallel i/o pins with interrupt capability 5- 20 parallel i/o port pb11 3-18 pb8 3-18, 3-29 port a 3-17, 5-17, 5-18 control register 3-17 data direction register (paddr) 3- 17 port b 3-17, 5-20 control register 3-18 parallel i/o ports 3-17 parameter ram 2-21 pb11 3-18 pb11 see dram refresh pb11 see parallel i/o port pb8 3-18, 3-29 pbcnt 3-18, 3-19 pbdat 3-20 pbddr 3-18, 3-20 pcm 4-2 pcm highway 5-14, 5-15 simode 4-2 periodic timer period calculation 3-23 physical layer serial interface pins 5-14 pin assignments 7-1 pin grid array 7-1 pit 2-11, 2-12, 3-22 as a real-time clock 3-24 period calculation 3-23 pit clock 2-12 pitr 3-24 pll 2-10 pll and oscillator changes to imp 2-5 clko drive options 2-6 three-state rclk1 2-6 three-state tclk1 2-6 pll clock divider 2-10 pll external components 2-9 pll pins pgnd 5-5 pinit 2-7
index motorola mc68lc302 reference manual index-5 pndat 3-20 pnddr 3-20 port a 3-17 port a pin functions 3-18 port a pin functions 3-18 port a/b parallel i/o 3-17 port b 3-18 port b pin functions 3-18 port n 3-19 padat 3-19 power dissipation 6-4 power pins 5-2 programmable data bus size switch 3-6 protocol parameters 2-20 pullup resistors 5-21 r rclk1 disabling 4-5 rclk1/l1clk 5-16 read-modify-write cycle 6-12 real-time clock 3-24 registers internal 2-22 interrupt in-service (isr) 3-16 interrupt pending (ipr) 3-15 port a control (pacnt) 3-17 data direction (paddr) 3-17 port b data direction register (pbddr) 3- 18 system control (scr) 2-4 reprogramming to uart mode or another protocol 4-20 reset 5-6, 5-20 instruction 2-3 reset smc memory structure 4-26 total system 2-3 revision number 2-20 ring oscillator 2-18 ringo 2-18 ringocr 2-19 ringoevr 2-20 rmc 3-4 rxd1/l1rxd 5-15 s sam 3-4, 3-28 sapr 3-13 scc 2-20 buffer descriptor 4-6 dsr 4-6 enable receiver 4-5 normal operation 4-5 scon 4-4 software operation 4-5 tin1/tin2 5-20 scc mode register 4-5 scc parameter ram 4-7 scc parameter ram memory map 4-7 sccs 4-4 scit 4-2 scm 4-5 scon 4-4 scp 2-20 serial communication port 4-25 scp port 5-19 scr 3-2 scr (system control register) 2-4 scr register bits 3-2 serial channels physical interface 4-2 serial communication controllers 4-4 serial communication port 4-25, 6-29 serial management controllers 4-26 smc1 receive buffer descriptor 4-26 smc1 transmit buffer descriptor 4-26 smc2 receive buffer descriptor 4-27 smc2 transmit buffer descripto 4-27 signals as 3-3, 3-25 berr 2-4, 3-3, 3-4, 3-5, 3-6 bg 3-28, 5-11 bgack 5-11 br 3-28, 3-29, 5-10 busw 2-1, 5-7 cd1 5-16 clko 5-4 cs 2-4, 3-3 cs0 3-26, 3-28, 5-21 cts1 5-17 discpu 3-28, 5-7
index index-6 mc68lc302 reference manual motorola dreq 3-11 dtack 3-4, 3-26, 3-28, 5-12 extal 5-2, 5-4 fc2-fc0 5-12 gci 5-15 halt 2-4, 5-6 iac 5-10 idl 5-15, 5-17 ilp0 5-11 irq1 5-12 nmsi2 5-17 nmsi3 5-18 pcm highway 5-15 port a 5-17, 5-18 port b 5-20 reset 2-3, 5-6, 5-20 rmc 3-4 rts1 5-17 scp 5-19 tin1/tin2 5-20 wdog 3-18, 5-20 xtal 5-4 simask 4-2, 4-4 simode 4-2 slow_go 2-10, 2-13, 2-14, 2-15 slow_go mode 2-14 smc 2-20 serial management controllers 4-26 smc memory structure 4-26 software operation 4-5 software watchdog timer 3-22 stand_by 2-13, 2-16 stand_by mode 2-13 stop 2-13, 2-16 stop mode 2-13 supervisor data space 2-3 system control registers (scr) 2-4 system clock imp 2-12 system control 3-1 system control bits 3-3 system control pins 5-5 system control register (scr) 3-2 system status bits 3-3 t tclk1 disabling 4-5 tclk1/l1sy0/sds1 5-16 tcn1, tcn2 3-21 tcr1, tcr2 3-21 ter1, ter2 3-21 thermal characteristics 6-2 timer pit 3-22 timer pins 5-19 timers 3-20 tin1/tin2 5-20 wdog 3-18, 3-22 tin1/tin2 5-20 tin1/tin2 see scc tmr1, tmr2 3-20 transparent controller 4-23 transparent event register 4-25 transparent mask register 4-25 transparent mode register 4-24 transparent receive buffer descriptor 4-24 transparent transmit buffer descriptor 4-25 trr1, trr2 3-21 ttl levels 5-2 txd1/l1txd 5-15 u uart controller 4-7 uart event register 4-9 uart mask register 4-9 uart memory map 4-7 uart mode register 4-8 uart receive buffer descriptor 4-8 uart transmit buffer descriptor 4-8 v vccsyn 2-12, 5-5 vco 2-10, 2-11 vector generation enable 3-5 w wake_up clock cycles, imp 2-13
index motorola mc68lc302 reference manual index-7 wake-up pb10 2-18 pit 2-18 pit event 2-18 watchdog (wdog) 3-18, 5-20 hardware 3-5 timer 3-22 watchdog (wdog) see signals watchdog (wdog) see timers wcn 3-22 weh (uds/a0) 5-9 wel (lds/ds) 5-10 write protect violation 3-3 wrr 3-22 x xfc 2-12, 5-5 xtal 5-4
index index-8 mc68lc302 reference manual motorola
this document contains information on a product under development. motorola reserves the right to change or discontinue this pr oduct without notice. errata and added information to mc68lc302 low power integrated multiprotocol processor reference manual rev 1 mc68lc302 motorola, 1996 microprocessor and memory technologies group semiconductor product information february 21, 1997 section 2?con?uration, clocking, low power modes, and internal memory map 1. scce2 register in section 2-24, in table 2-6, the scce2 register should be 8 bits wide, not 16 bits as shown. section 3 - sytstem integration block 1. periodic interrupt timer equation in section 3.7.4.2, in the periodic interrupt timer period equation, the "+1" should be carried through the equations. section 5 - signal description 1. bus request signal description in section 5.8, the bus request signal is shown incorrectly in figure 5-7 an d the description below the figure is incorrect. the pin is shown as bidirectional, but should be an out put only. the description shoud read, ?his signal is an open-drain output request signal from the idma and sdma when the internal ec000 core is disabled. 2. port a / bootstrap mode description in section 5.14 in the ?ote?section, ?o enable boot from scc2?should be replaced with ?o enable boot from scc1.?the bootstrap mode is only available on scc1.
motorola mc68lc302 reference manual errata 2 section 6- electrical characteristics 1. thermal characteristic values ( ja , jc ) in section 6.2 in the thermal characteristic table, the value for ja should read 52.8, replacing tbd; also, the value for jc should read 10.4, replacing tbd. 2. junction temperature (tj) equation in section 6.2, the junction temperature equation should read: tj = 70c + (5.25v*50ma*52.8c/w) = 83.9c. 3. ac electrical specification changes at 3.3v in section 6.8 in the ac electrical specification table, all information is for 5.0v only. the only value which changes at 3.3v is spec 47, the asynchronous input setup time (t asi ). this value should be 12ns, instead of 10ns, at both 16.67 and 20mhz. 25mhz is not sup- ported at 3.3v.
semiconductor product information literature distribution centers: usa/europe: motorola literature distribution; p.o. box 20912, arizona 85036. japan: nippon motorola ltd.; 4-32-1, nishi-gotanda, shinagawa-ku, tokyo 141 japan. asia-pacific: motorola semiconductors h.k. ltd.; silicon harbour center, no. 2 dai king street, tai po industrial estate, motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, represe ntation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the applicati on or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "typical" para meters can and do vary in different applications. all operating parameters, including "typicals" must be validated for each customer application by customer's tec hnical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authoriz ed for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any othe r application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola prod ucts for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of persona l injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer.
order this document by mc68lc302/d this document contains information on a product under development. motorola reserves the right to change or discontinue this product without notice. product brief low cost integrated multiprotocol processor mc68lc302 motorola, 1995 microprocessor and memory technologies group semiconductor product information motorola introduces the low cost version of the well-known mc68302 integrated multiprotocol processor (imp). it will be known as the mc68lc302, and will expand a family of devices based on the mc68302. some features and pins have been removed while other features have been enhanced as compared to the original mc68302. simply put, the mc68lc302 is a traditional mc68302 with a new static 68000 core, a new timer and low power modes, but without the third serial communication controller (scc). it is packaged in a low profile 100 tqfp that requires less board space than the regular mc68302, as well as making it suitable for use in height restricted applications such as pcmcia. . peripheral bus 68000 system bus 4 sdma channels interrupt controller risc controller static m68000 core 1 general- purpose dma channel 3 timers 4 chip selects pio system control ram / rom scp + 2 smcs 1152 bytes dual-port ram 2 serial channels (sccs) pit low power control 20 address 8/16 data 68lc302
2 mc68lc302 product information motorola features the features of the mc68lc302 are as follows. bold face items show major differences from the mc68302. on-chip static 68000 core supporting a 16- or 8-bit m68000 family system sib including: independent direct memory access (idma) controller interrupt controller with two modes of operation parallel input/output (i/o) ports, some with interrupt capability on-chip 1152-byte dual-port ram three timers including a watchdog timer new periodic interrupt timer (pit) four programmable chip-select lines with wait-state generator logic programmable address mapping of the dual-port ram and imp registers on-chip clock generator with output signal on-chip pll allows operation with 32 khz or 4 mhz crystals glueless interface to eprom, sram, flash eprom, and eeprom allows boot in 8-bit mode, and running switch to 16-bit mode system control: system status and control logic disable cpu logic (slave mode operation) hardware watchdog new low-power (standby) modes with wake-up from two pins or pit freeze control for debugging (available only in the pga package) dram refresh controller cp including: main controller (risc processor) two independent full-duplex serial communications controllers (sccs) supporting various protocols: high-level/synchronous data link control (hdlc/sdlc) universal asynchronous receiver transmitter (uart) binary synchronous communication (bisync) transparent modes autobaud support v.110 rate adaption four serial dma channels for the two sccs flexible physical interface accessible by sccs including: motorola interchip digital link (idl) general circuit interface (gci, also known as iom-2 1 ) pulse code modulation (pcm) highway interface nonmultiplexed serial interface (nmsi) implementing standard modem signals scp for synchronous communication two serial management controllers (smcs) to support idl and gci auxiliary channels 100 pin thin quad flat pack (tqfp) packaging 1. iom is a trademark of siemens ag
motorola mc68lc302 product information 3 mc68lc302 applications the mc68lc302 excels in several applications areas. first, any application using the mc68302,but not needing all three serial channels is a potential candidate for the mc68lc302. note however, that the mc68lc302 sacrifices most of the provision for external bus mastership, thus the mc68lc302 may not be appropriate where the mc68302 is used as part of larger systems. second, the mc68lc302 excels in low power and portable applications. the inclusion of a static 68000 core, coupled with the low power modes built into the device make it ideal for handheld, or other low power applications. the new 32 khz or 4 mhz pll option greatly reduces the total power budget of the designer? board, and allows the mc68lc302 to be an effective device in low power systems. the mc68lc302 can then optionally generate a full frequency clock for use by the rest of the board. during low power modes, the new periodic interrupt timer (pit) allows the device to awaken at regular intervals. in addition, two pins can awaken the device from low power modes. third, given that the mc68lc302 is packaged in a 100tqfp package, it allows the mc68lc302 to be used in space critical applications, as well as height critical applications such as pcmcia cards. fourth, since the disable cpu mode (also known as slave mode) is still retained, the mc68lc302 can function as a fully intelligent dma-driven peripheral chip containing serial channels, timers, chip selects, etc. differences between the mc68lc302 and mc68302 the mc68lc302 has some specific differences from the mc68302. even though the functionality of the processor and the peripherals remain the same, some of the flexibility has been removed due to the pin reduction from 132 on the original mc68302, to 100 pins on the mc68lc302. the following features have been removed or modified from the mc68302 in order to make the mc68lc302 possible. scc3 and its baud rate generator (brg3) are removed. external masters are not able to take the bus away from the mc68lc302 through the normal bus arbi- tration scheme as these pins no longer exist. an external master can still maintain bus mastership through a simple scheme using the halt pin. this restriction does not apply when using the mc68lc302 in cpu disabled mode (slave mode), in which case br , bg , and bgack are all available. although the independent dma (idma) is still available, the external idma request pins (dreq , dack , and done ) have been eliminated. idma transfers can only originate under cpu control. four address lines have been eliminated, giving a total of 20 address lines. however, the mc68lc302 supports more than a 1 mb addressing range, since each of the four chip selects still decodes a 24-bit address. this allows addressing a total of 4 mb. since the function code pins and avec have been removed, interrupt acknowledgment to external de- vices is only provided on levels one, six, and seven. the ddcmp protocol is no longer available for the sccs. the total list of pins removed is: a23-a20, fc2-fc0, avec , rmc , iac , berr , br , bg , bgack , bclr , iack1 , iack6 , iack7 , dreq , dack , done , brg1, frz , tout1 , nc1, nc3, tclk3, rts3 , cts3 , cd3 , plus 5 power and ground pins.
4 mc68lc302 product information motorola the scp pins are now muxed with pa8, pa9, and pa10. the txd3, rxd3, and rclk3 functions asso- ciated with scc3 are eliminated. the uds , lds , and r/w pins are not available except in slave mode, where they replace the ipl2-0 pins. instead, the new pins weh , wel , and oe have been defined for glueless interfacing to memory. pa12 is now muxed with the modclk pin, which is associated with the 32 khz or 4 mhz pll. the mod- clk pin is sampled after reset, and then becomes pa12. new vccsyn, gndsyn, and xfc pins have been added in support of the on-chip pll. for purposes of emulation and development support only, a special 132 pga version is supported. this version adds back the fc2-0, iac , frz , and avec pins. the fc2-0 pins allow bus cycles to be distin- guished between program and data accesses, interrupt cycles, etc. the iac , frz , and avec pins are provided so that emulation vendors can quickly retrofit their existing mc68302 emulator designs to sup- port the mc68lc302.
motorola mc68lc302 product information 5 mc68lc302 pin description note: pins in parenthesis () show functionality that is only available in slave mode when the cpu is disabled by asserting the discpu pin. tclk1/l1sy0/sds1 brg2/sds2/pa7 wel /we (lds/ds) extal xfc xtal a1-a19 data bus mc68lc302 bus control interrupt control chip select reset halt busw discpu ipl0 /irq1 (br) ipl2 /irq7 (bg) ipl1 /irq6 (bgack) cs0 /iout2 cs3 -cs1 address bus rxd1/l1rxd rclk1/l1clk txd1/l1txd cd1 /l1sy1 cts1 /l1gr rts1 /l1rq/gcidcl iqgnd(2) system control iqvdd(2) clko clock rxd2/pa0 rclk2/pa2 txd2/pa1 tclk2/pa3 cts2 /pa4 rts2 /pa5 cd2 /pa6 sprxd/pa8 spclk/pa10 sptxd/pa9 modclkpa12 tin1/pb3 tin2/pb5 tout2 /pb6 wdog /pb7 pb8 d0-d15 nmsi1/ isdn i/f nmsi2/ paio paio/ scp timer/pbio pb9 pb10 pb11 signals as weh /a0 (uds/a0) dtack oe (r/w )
literature distribution centers: usa: motorola literature distribution; p.o. box 20912, arizona 85036. europe: motorola ltd.; european literature centre; 88 tanners drive, blakelands, milton keynes, mk14 5bp, england. japan: nippon motorola ltd.; 4-32-1, nishi-gotanda, shinagawa-ku, tokyo 141 japan. asia-pacific: motorola semiconductors h.k. ltd.; silicon harbour center, no. 2 dai king street, tai po industrial estate, tai po, n.t., hong kong. motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "typical" parameters can and do vary in different applications. all operating parameters, including "typicals" must be validated for each customer application by customer's technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. semiconductor product information table 1. mc68lc302 ordering information package type operating voltage frequency (mhz) temperature order number pin grid array (rc suffix) 5v 20 0 c to 70 c mc68lc302rc20 thin quad flat pack (pu suffix) 5v 5v 5v 5v 16.67 16.67 20 20 0 c to 70 c ?0 c to +85 c 0 c to 70 c ?0 c to +85 c MC68LC302PU16 mc68lc302cpu16 mc68lc302pu20 tbd thin quad flat pack (pu suffix) 3.3v 3.3v 3.3v 3.3v 16.67 16.67 20 20 0 c to 70 c ?0 c to +85 c 0 c to 70 c ?0 c to +85 c MC68LC302PU16v mc68lc302cpu16v tbd tbd table 2. documentation document title order number contents mc68302 user's manual mc68302um/ad detailed information for design m68000 family programmer's reference manual m68000pm/ad m68000 family instruction set the 68k source br729/d independent vendor listing supporting soft- ware and development tools the 68lc302 addendum describes the differences between the mc68302 and the mc68lc302
semiconduc tor products sector networking and computing systems group networking and communications system division pcn: 86lc302 fab transfer to tsc effective date: 07-aug-00 motorola is pleased to announce the expansion of our mc68lc302 manufacturing capabilities with the use of our tsc8 facility in japan. this means the 68lc302 will have two fab sources, mos11 and tsc8. the tsc8 facility is fully qualified for mc production of the 68lc302 and will use the same database as our current production in austin texas. parts produced in japan will have the mask set k38e and have no functional differences from our j29a mask production in mos11 austin, texas. the majority of lc302 production will be produced in tsc8. we have created special sample packs that will specify the k38e mask devices produced in tsc8 to facilitate customers qualifying this second manufacturing site. the below part numbers should be used for ordering the tsc8 sample packs: km68lc302pu20vct 68lc302 tqfp 3.3v 20mhz kmc68lc302pu20ct 68lc302 tqfp 5.0v 20mhz kmc68lc302pu25ct 68lc302 tqfp 5.0v 25mhz please note that the the production part numbers will now change. the production part numbers will be, e.g.: mc68lc302pu20vct 68lc302 tqfp 3.3v 20mhz mc68lc302pu20ct 68lc302 tqfp 5.0v 20mhz mc68lc302pu25ct 68lc302 tqfp 5.0v 25mhz all new 68lc302 volume production orders must use the ?ct? suffix part numbers. additionally, most existing 68lc302 orders on backlog will need to change to the new ?ct? suffix part numbers. we will be ready to ship ?ct? product starting august 1, 2000. the ?ct? part numbers reflect that die can be sourced from either tsc8 or mos11, but please note the majority of lc302 production, if not all, will be produced in tsc8. qualification plan qualification of mc68lc302 in tsc8 (k38e) the tsc8 mc68lc302 device, mask set k38e, has successfully completed r&qa qualification. this device is currently manufactured as j29a in mos11 on the 82.5% udr2/cdr1 process (0.57um tlm) and assembled in the 100 lead tqfp (pu) package in shc. the process used in
tsc8 is also 82.5% udr2/udr1 (0.57um tlm). all of these technologies are fully qualified. esd and latch-up performance for this device in tsc8 has been confirmed to be comparable to current mos11 material. an electrical characterization was also performed. all key electrical parameters are meeting specifications. qualification results are summarized below. the qualification of the mc63lc302 (k38e) in tsc8 required a reduced data set based on data taken during the mc68360 (k36e) qualification, which is similar in design and utilizes the same process at tsc8. 68lc302 (82.5 udr2/cdr in mos11 - 82.5 udr2/udr in tsc8) - lifetest, 168 hrs: one lot, 77 pcs - esd and latch-up: three lots, 12 pcs each reliability data summary mc68lc302 (k38e) qualification data: stress results (#fails/#devices) lifetest (6.0v, 125c) c25508a 0/89 @168 hours esd human body model (2kv) c25781a 0/3 c25794a 0/3 c25508.17a 0/3 esd machine model (200v) c25781a 0/3 c25794a 0/3 c25508.17a 0/3 latchup (200ma) c25781a 0/3 c25794a 0/3 c25508.17a 0/3 electro static discharge life test lot hours room temp hot temp low temp comment c25508a 168 89/90 89/90 1 failed unit bent leads human body model (new) 2kv max
lot voltage room temp hot temp low temp c25781a 1kv 0/3 0/3 0/3 c25781a 1.5kv 0/3 0/3 0/3 c25781a 2kv** 0/3 0/3 0/3 c25794a 1kv 0/3 0/3 0/3 c25794a 1.5kv 0/3 0/3 0/3 c25794a 2kv** 0/3 0/3 0/3 c25508.17a 2kv** 0/3 0/3 0/3 **needed for standard requirement machine model (new) 2kv max lot voltage room temp hot temp low temp c25781a 100v 0/3 0/3 0/3 c25781a 200v 0/3 0/3 0/3 c25794a 100v 0/3 0/3 0/3 c25794a 200v 0/3 0/3 0/3 c25508 200v 0/3 0/3 0/3 latch up lot current room temp high temp low temp c25781a 100ma 0/3 0/3 0/3 c25781a 200ma 0/3 0/3 0/3 c25794a 200ma 0/3 0/3 0/3 c25508.17a 200ma 0/3 0/3 0/3 electrical characteristic summary there are no signifacant electrical changes in either ac or dc specs. changed part identification we have created special sample packs that will specify the k38e mask devices produced in tsc8 to facilitate customers qualifying this second manufacturing site. the below part numbers should be used for ordering the tsc8 sample packs: km68lc302pu20vct 68lc302 tqfp 3.3v 20mhz kmc68lc302pu20ct 68lc302 tqfp 5.0v 20mhz kmc68lc302pu25ct 68lc302 tqfp 5.0v 25mhz please note that the the production part numbers will now change. the production part numbers will be, e.g.: mc68lc302pu20vct 68lc302 tqfp 3.3v 20mhz mc68lc302pu20ct 68lc302 tqfp 5.0v 20mhz mc68lc302pu25ct 68lc302 tqfp 5.0v 25mhz all new 68lc302 volume production orders must use the ?ct? suffix part numbers. additionally,
most existing 68lc302 orders on backlog will need to change to the new ?ct? suffix part numbers. we will be ready to ship ?ct? product starting august 1, 2000. the ?ct? part numbers reflect that die can be sourced from either tsc8 or mos11, but please note the majority of lc302 production, if not all, will be produced in tsc8. afected device list part km68lc302pu20vct kmc68lc302pu20c kmc68lc302pu20ct kmc68lc302pu20vc kmc68lc302pu25c kmc68lc302pu25ct mc68lc302cpu16c mc68lc302cpu16vc mc68lc302cpu20c mc68lc302cpu20vc MC68LC302PU16c MC68LC302PU16vc mc68lc302pu20c mc68lc302pu20vc mc68lc302pu25c sc530204lcpu16b spaklc302pu16b spaklc302pu16vb spaklc302pu20b spaklc302pu20vb spaklc302pu25b xc68lc302cpu16b xc68lc302cpu16vb xc68lc302cpu20b xc68lc302cpu20vb xc68lc302pu16b xc68lc302pu16vb xc68lc302pu20b xc68lc302pu20vb xc68lc302pu25b

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